| Commit message (Expand) | Author | Age | Files | Lines |
|---|
| * | Second attempt at providing correct encodings for Thumb2 binary operators. | Owen Anderson | 2010-11-14 | 1 | -51/+105 |
| * | Comment out the defms until they're activated. | Bill Wendling | 2010-11-13 | 1 | -1/+3 |
| * | Add uses of the *_ldst_multi multiclasses. These aren't used yet. | Bill Wendling | 2010-11-13 | 1 | -0/+10 |
| * | Convert the modes to lower case. | Bill Wendling | 2010-11-13 | 1 | -4/+4 |
| * | Add *_ldst_mult multiclasses to the ARM back-end. These will be used in the | Bill Wendling | 2010-11-13 | 1 | -0/+64 |
| * | Conditional moves are slightly more expensive than moves. | Evan Cheng | 2010-11-13 | 1 | -5/+1 |
| * | Add conditional move of large immediate. | Evan Cheng | 2010-11-13 | 1 | -1/+9 |
| * | Revert r118939 while I work out why it broke some buildbots. | Owen Anderson | 2010-11-12 | 1 | -65/+52 |
| * | Attemt to provide correct encodings for Thumb2 binary operators. | Owen Anderson | 2010-11-12 | 1 | -52/+65 |
| * | Add conditional mvn instructions. | Evan Cheng | 2010-11-12 | 1 | -3/+16 |
| * | First stab at providing correct Thumb2 encodings, start with adc. | Owen Anderson | 2010-11-12 | 1 | -19/+66 |
| * | Fix @llvm.prefetch isel. Selecting between pld / pldw using the first immedia... | Evan Cheng | 2010-11-04 | 1 | -15/+15 |
| * | Fix preload instruction isel. Only v7 supports pli, and only v7 with mp exten... | Evan Cheng | 2010-11-03 | 1 | -22/+21 |
| * | Add support to match @llvm.prefetch to pld / pldw / pli. rdar://8601536. | Evan Cheng | 2010-11-03 | 1 | -28/+21 |
| * | Break ARM addrmode4 (load/store multiple base address) into its constituent | Jim Grosbach | 2010-11-03 | 1 | -14/+14 |
| * | Completely reject instructions that have an operand in their | Chris Lattner | 2010-11-02 | 1 | -3/+9 |
| * | The T2 extract/pack instructions are only valid in Thumb2 mode. Mark the | Jim Grosbach | 2010-11-01 | 1 | -12/+14 |
| * | two changes: make the asmmatcher generator ignore ARM pseudos properly, | Chris Lattner | 2010-10-31 | 1 | -2/+2 |
| * | reapply r117858 with apparent editor malfunction fixed (somehow I | Chris Lattner | 2010-10-31 | 1 | -3/+5 |
| * | revert r117858 while I check out a failure I missed. | Chris Lattner | 2010-10-31 | 1 | -5/+3 |
| * | the asm matcher can't handle operands with modifiers (like ${foo:bar}). | Chris Lattner | 2010-10-31 | 1 | -3/+5 |
| * | Overhaul memory barriers in the ARM backend. Radar 8601999. | Bob Wilson | 2010-10-30 | 1 | -66/+17 |
| * | Remove hard tab characters. | Jim Grosbach | 2010-10-29 | 1 | -3/+3 |
| * | Re-commit 117518 and 117519 now that ARM MC test failures are out of the way. | Evan Cheng | 2010-10-28 | 1 | -12/+12 |
| * | Revert 117518 and 117519 for now. They changed scheduling and cause MC tests ... | Evan Cheng | 2010-10-28 | 1 | -12/+12 |
| * | - Assign load / store with shifter op address modes the right itinerary classes. | Evan Cheng | 2010-10-28 | 1 | -12/+12 |
| * | imm12 operands aren't Thumb2 only, so rename the printer helper function. | Jim Grosbach | 2010-10-25 | 1 | -1/+1 |
| * | Remove unused ARMISD::AND selection DAG node. | Bob Wilson | 2010-10-15 | 1 | -4/+0 |
| * | Tweak the ARM backend to use the RRX mnemonic instead of the 'mov a, b, rrx' | Jim Grosbach | 2010-10-14 | 1 | -1/+1 |
| * | A few 80 column fixes. | Jim Grosbach | 2010-10-13 | 1 | -2/+2 |
| * | Allow use of the 16-bit literal move instruction in CMOVs for Thumb2 mode. | Jim Grosbach | 2010-10-07 | 1 | -0/+11 |
| * | Clean up MOVi32imm and t2MOVi32imm pseudo instruction definitions. | Jim Grosbach | 2010-10-06 | 1 | -3/+3 |
| * | - Add TargetInstrInfo::getOperandLatency() to compute operand latencies. This | Evan Cheng | 2010-10-06 | 1 | -5/+6 |
| * | Nuke the rest of the :comment references | Jim Grosbach | 2010-10-01 | 1 | -2/+1 |
| * | The asm strings are never used at all, so just nuke 'em entirely. | Jim Grosbach | 2010-09-30 | 1 | -4/+2 |
| * | Go ahead and jump! | Jim Grosbach | 2010-09-30 | 1 | -14/+2 |
| * | ARM instruction itinerary fixes: | Evan Cheng | 2010-09-30 | 1 | -90/+100 |
| * | Model Cortex-a9 load to SUB, RSB, ADD, ADC, SBC, RSC, CMN, MVN, or CMP | Evan Cheng | 2010-09-29 | 1 | -2/+2 |
| * | Separate itinerary classes for mvn from mov; for tst / teq from cmp / cmn. | Evan Cheng | 2010-09-29 | 1 | -10/+20 |
| * | Assign bitwise binary instructions different itinerary classes from ALU instr... | Evan Cheng | 2010-09-29 | 1 | -22/+33 |
| * | More pseudo instruction scheduling itinerary fixes. | Evan Cheng | 2010-09-24 | 1 | -1/+1 |
| * | Fix scheduling itinerary for pseudo mov immediate instructions which expand i... | Evan Cheng | 2010-09-24 | 1 | -3/+3 |
| * | Revert r114703 and r114702, removing the isConditionalMove flag from instruct... | Owen Anderson | 2010-09-23 | 1 | -2/+2 |
| * | Add isConditionalMove bits to X86 and ARM instructions. | Owen Anderson | 2010-09-23 | 1 | -2/+2 |
| * | fix a long standing wart: all the ComplexPattern's were being | Chris Lattner | 2010-09-21 | 1 | -1/+2 |
| * | Fix LDM_RET schedule itinery. | Evan Cheng | 2010-09-08 | 1 | -1/+2 |
| * | remove some dead code. t2addrmode_imm8s4 is never used in a | Chris Lattner | 2010-09-05 | 1 | -2/+1 |
| * | temporarily revert r112664, it is causing a decoding conflict, and | Chris Lattner | 2010-09-01 | 1 | -12/+0 |
| * | We have a chance for an optimization. Consider this code: | Bill Wendling | 2010-08-31 | 1 | -0/+12 |
| * | Use the existing T2I_bin_s_irs pattern instead of creating T2I_bin_sw_irs, which | Bill Wendling | 2010-08-30 | 1 | -48/+2 |
