| Commit message (Expand) | Author | Age | Files | Lines |
|---|
| * | Some enhancements for memcpy / memset inline expansion. | Evan Cheng | 2012-12-10 | 1 | -2/+4 |
| * | The code pattern "imm0_255_neg" is used for checking if an immediate value is... | Nadav Rotem | 2012-11-14 | 1 | -6/+7 |
| * | Disable the Thumb no-return call optimization: | Evan Cheng | 2012-11-10 | 1 | -14/+0 |
| * | ARM: Better disassembly for pc-relative LDR. | Jim Grosbach | 2012-10-30 | 1 | -1/+1 |
| * | Fix ARM's b.w instruction for thumb 2 and the encoding T4. The branch target | Kevin Enderby | 2012-10-29 | 1 | -2/+2 |
| * | Fix a miscompilation caused by a typo. When turning a adde with negative value | Evan Cheng | 2012-10-24 | 1 | -1/+1 |
| * | Add LLVM support for Swift. | Bob Wilson | 2012-09-29 | 1 | -12/+14 |
| * | Remove predicated pseudo-instructions. | Jakob Stoklund Olesen | 2012-09-05 | 1 | -58/+0 |
| * | Patch to implement UMLAL/SMLAL instructions for the ARM architecture | Arnold Schwaighofer | 2012-09-04 | 1 | -6/+25 |
| * | Revert r162713: "Add ATOMIC_LDR* pseudo-instructions to model atomic_load on ... | Jakob Stoklund Olesen | 2012-08-28 | 1 | -54/+14 |
| * | Add ATOMIC_LDR* pseudo-instructions to model atomic_load on ARM. | Jakob Stoklund Olesen | 2012-08-27 | 1 | -14/+54 |
| * | Explicitly mark LEApcrel pseudos with hasSideEffects. | Jakob Stoklund Olesen | 2012-08-24 | 1 | -0/+1 |
| * | Add ADD and SUB to the predicable ARM instructions. | Jakob Stoklund Olesen | 2012-08-16 | 1 | -0/+27 |
| * | Handle ARM MOVCC optimization in PeepholeOptimizer. | Jakob Stoklund Olesen | 2012-08-16 | 1 | -1/+1 |
| * | Fold predicable instructions into MOVCC / t2MOVCC. | Jakob Stoklund Olesen | 2012-08-15 | 1 | -1/+1 |
| * | Add missing Rfalse operand to the predicated pseudo-instructions. | Jakob Stoklund Olesen | 2012-08-15 | 1 | -6/+9 |
| * | Revert 161581: Patch to implement UMLAL/SMLAL instructions for the ARM | Arnold Schwaighofer | 2012-08-12 | 1 | -25/+6 |
| * | Patch to implement UMLAL/SMLAL instructions for the ARM architecture | Arnold Schwaighofer | 2012-08-09 | 1 | -6/+25 |
| * | ARM: More InstAlias refactors to use #NAME#. | Jim Grosbach | 2012-08-02 | 1 | -42/+27 |
| * | ARM: Refactor instaliases using TableGen support for #NAME#. | Jim Grosbach | 2012-08-02 | 1 | -31/+23 |
| * | Fix #13241, a bug around shift immediate operand for ARM instruction ADR. | Jiangning Liu | 2012-08-02 | 1 | -0/+1 |
| * | Remove variable_ops from ARM call instructions. | Jakob Stoklund Olesen | 2012-07-13 | 1 | -2/+2 |
| * | Do not attempt to use ROR for Thumb1. | Bob Wilson | 2012-07-02 | 1 | -2/+2 |
| * | (sub X, imm) gets canonicalized to (add X, -imm) | Evan Cheng | 2012-06-23 | 1 | -0/+7 |
| * | ARM: Define generic HINT instruction. | Jim Grosbach | 2012-06-18 | 1 | -15/+12 |
| * | This change handles a another case for generating the bic instruction | Joel Jones | 2012-06-18 | 1 | -0/+31 |
| * | Re-enable the CMN instruction. | Bill Wendling | 2012-06-11 | 1 | -13/+57 |
| * | Revert commit r157966 | Joel Jones | 2012-06-05 | 1 | -24/+0 |
| * | This change handles a another case for generating the bic instruction | Joel Jones | 2012-06-04 | 1 | -0/+24 |
| * | Thumb2: RSB source register should be rGRP not GPRnopc. | Jim Grosbach | 2012-05-21 | 1 | -4/+4 |
| * | Fix the encoding of the armv7m (MClass) for MSR APSR writes which was missing | Kevin Enderby | 2012-05-17 | 1 | -2/+2 |
| * | ARM: Add a few missing add->sub aliases w/ 'w' suffix. | Jim Grosbach | 2012-05-01 | 1 | -0/+11 |
| * | - thumbv6 shouldn't imply +thumb2. Cortex-M0 doesn't suppport 32-bit Thumb2 | Evan Cheng | 2012-04-27 | 1 | -6/+6 |
| * | Tidy up. 80 columns, whitespace, et. al. | Jim Grosbach | 2012-04-23 | 1 | -4/+4 |
| * | Fix a few more places in the ARM disassembler so that branches get | Kevin Enderby | 2012-04-12 | 1 | -0/+1 |
| * | ARM fix cc_out operand handling for t2SUBrr instructions. | Jim Grosbach | 2012-04-10 | 1 | -1/+2 |
| * | Deduplicate ARM call-related instructions. | Jakob Stoklund Olesen | 2012-04-06 | 1 | -21/+3 |
| * | ARM assembly aliases for add negative immediates using sub. | Jim Grosbach | 2012-04-05 | 1 | -5/+23 |
| * | Implement ARMBaseInstrInfo::commuteInstruction() for MOVCCr. | Jakob Stoklund Olesen | 2012-04-04 | 1 | -0/+2 |
| * | ARM assembly 'cmp lr, #0' should not encode using 'cmn'. | Jim Grosbach | 2012-03-29 | 1 | -1/+2 |
| * | Change conditional instructions definitions, e.g. ANDCC, ARMPseudoExpand and ... | Evan Cheng | 2012-03-20 | 1 | -32/+23 |
| * | ARM fix silly typo in optional operand alias. | Jim Grosbach | 2012-03-16 | 1 | -1/+1 |
| * | ARM optional operand on MRC/MCR assembly instructions. | Jim Grosbach | 2012-03-16 | 1 | -0/+12 |
| * | Re-commit r151623 with fix. Only issue special no-return calls if it's a dire... | Evan Cheng | 2012-02-28 | 1 | -0/+32 |
| * | Revert r151623 "Some ARM implementaions, e.g. A-series, does return stack pre... | Daniel Dunbar | 2012-02-28 | 1 | -32/+0 |
| * | Some ARM implementaions, e.g. A-series, does return stack prediction. That is, | Evan Cheng | 2012-02-28 | 1 | -0/+32 |
| * | Thumb2 asm aliases for wide bitwise w/ immediate instructions. | Jim Grosbach | 2012-02-24 | 1 | -0/+9 |
| * | Switch ARM target to register masks. | Jakob Stoklund Olesen | 2012-02-24 | 1 | -3/+1 |
| * | Optimize a couple of common patterns involving conditional moves where the false | Evan Cheng | 2012-02-23 | 1 | -0/+38 |
| * | Emacs-tag and some comment fix for all ARM, CellSPU, Hexagon, MBlaze, MSP430,... | Jia Liu | 2012-02-18 | 1 | -1/+1 |
