external_llvm.git - Unnamed repository; edit this file 'description' to name the repository.

	Commit message (Expand)	Author	Age	Files	Lines
*	ARM: fix literal load with positive offset encoding	Amaury de la Vieuville	2013-06-18	1	-3/+3
*	ARM: add operands pre-writeback variants when needed	Amaury de la Vieuville	2013-06-18	1	-18/+31
*	ARM: fix thumb literal loads decoding	Amaury de la Vieuville	2013-06-18	1	-4/+12
*	ARM: fix thumb coprocessor instruction with pre-writeback disassembly	Amaury de la Vieuville	2013-06-14	1	-1/+1
*	ARM: ISB cannot be passed the same options as DMB	Amaury de la Vieuville	2013-06-10	1	-1/+1
*	ARM sched model: Add branch thumb2 instructions	Arnold Schwaighofer	2013-06-06	1	-11/+15
*	ARM sched model: Add preload thumb2 instructions	Arnold Schwaighofer	2013-06-06	1	-3/+6
*	ARM sched model: Add more ALU and CMP thumb2 instructions	Arnold Schwaighofer	2013-06-06	1	-52/+86
*	Revert series of sched model patches until I figure out what is going on.	Arnold Schwaighofer	2013-06-04	1	-107/+66
*	ARM sched model: Add branch thumb2 instructions	Arnold Schwaighofer	2013-06-04	1	-11/+15
*	ARM sched model: Add preload thumb2 instructions	Arnold Schwaighofer	2013-06-04	1	-3/+6
*	ARM sched model: Add more ALU and CMP thumb2 instructions	Arnold Schwaighofer	2013-06-04	1	-52/+86
*	Tidy some register classes for ARM and Thumb	JF Bastien	2013-05-29	1	-1/+1
*	ARM: Fix encoding of hint instruction for Thumb.	Quentin Colombet	2013-04-26	1	-11/+6
*	ARM: Correct printing of pre-indexed operands.	Quentin Colombet	2013-04-12	1	-1/+1
*	ARM: Make "SMC" instructions conditional on new TrustZone architecture feature.	Tim Northover	2013-04-10	1	-1/+2
*	ARM: Convenience aliases for 'srs*' instructions.	Jim Grosbach	2013-02-23	1	-0/+7
*	Some enhancements for memcpy / memset inline expansion.	Evan Cheng	2012-12-10	1	-2/+4
*	The code pattern "imm0_255_neg" is used for checking if an immediate value is...	Nadav Rotem	2012-11-14	1	-6/+7
*	Disable the Thumb no-return call optimization:	Evan Cheng	2012-11-10	1	-14/+0
*	ARM: Better disassembly for pc-relative LDR.	Jim Grosbach	2012-10-30	1	-1/+1
*	Fix ARM's b.w instruction for thumb 2 and the encoding T4. The branch target	Kevin Enderby	2012-10-29	1	-2/+2
*	Fix a miscompilation caused by a typo. When turning a adde with negative value	Evan Cheng	2012-10-24	1	-1/+1
*	Add LLVM support for Swift.	Bob Wilson	2012-09-29	1	-12/+14
*	Remove predicated pseudo-instructions.	Jakob Stoklund Olesen	2012-09-05	1	-58/+0
*	Patch to implement UMLAL/SMLAL instructions for the ARM architecture	Arnold Schwaighofer	2012-09-04	1	-6/+25
*	Revert r162713: "Add ATOMIC_LDR* pseudo-instructions to model atomic_load on ...	Jakob Stoklund Olesen	2012-08-28	1	-54/+14
*	Add ATOMIC_LDR* pseudo-instructions to model atomic_load on ARM.	Jakob Stoklund Olesen	2012-08-27	1	-14/+54
*	Explicitly mark LEApcrel pseudos with hasSideEffects.	Jakob Stoklund Olesen	2012-08-24	1	-0/+1
*	Add ADD and SUB to the predicable ARM instructions.	Jakob Stoklund Olesen	2012-08-16	1	-0/+27
*	Handle ARM MOVCC optimization in PeepholeOptimizer.	Jakob Stoklund Olesen	2012-08-16	1	-1/+1
*	Fold predicable instructions into MOVCC / t2MOVCC.	Jakob Stoklund Olesen	2012-08-15	1	-1/+1
*	Add missing Rfalse operand to the predicated pseudo-instructions.	Jakob Stoklund Olesen	2012-08-15	1	-6/+9
*	Revert 161581: Patch to implement UMLAL/SMLAL instructions for the ARM	Arnold Schwaighofer	2012-08-12	1	-25/+6
*	Patch to implement UMLAL/SMLAL instructions for the ARM architecture	Arnold Schwaighofer	2012-08-09	1	-6/+25
*	ARM: More InstAlias refactors to use #NAME#.	Jim Grosbach	2012-08-02	1	-42/+27
*	ARM: Refactor instaliases using TableGen support for #NAME#.	Jim Grosbach	2012-08-02	1	-31/+23
*	Fix #13241, a bug around shift immediate operand for ARM instruction ADR.	Jiangning Liu	2012-08-02	1	-0/+1
*	Remove variable_ops from ARM call instructions.	Jakob Stoklund Olesen	2012-07-13	1	-2/+2
*	Do not attempt to use ROR for Thumb1.	Bob Wilson	2012-07-02	1	-2/+2
*	(sub X, imm) gets canonicalized to (add X, -imm)	Evan Cheng	2012-06-23	1	-0/+7
*	ARM: Define generic HINT instruction.	Jim Grosbach	2012-06-18	1	-15/+12
*	This change handles a another case for generating the bic instruction	Joel Jones	2012-06-18	1	-0/+31
*	Re-enable the CMN instruction.	Bill Wendling	2012-06-11	1	-13/+57
*	Revert commit r157966	Joel Jones	2012-06-05	1	-24/+0
*	This change handles a another case for generating the bic instruction	Joel Jones	2012-06-04	1	-0/+24
*	Thumb2: RSB source register should be rGRP not GPRnopc.	Jim Grosbach	2012-05-21	1	-4/+4
*	Fix the encoding of the armv7m (MClass) for MSR APSR writes which was missing	Kevin Enderby	2012-05-17	1	-2/+2
*	ARM: Add a few missing add->sub aliases w/ 'w' suffix.	Jim Grosbach	2012-05-01	1	-0/+11
*	- thumbv6 shouldn't imply +thumb2. Cortex-M0 doesn't suppport 32-bit Thumb2	Evan Cheng	2012-04-27	1	-6/+6