| Commit message (Expand) | Author | Age | Files | Lines |
|---|
| * | Add the "isCompare" attribute to the defm instead of each individual instr. | Bill Wendling | 2010-08-19 | 1 | -3/+1 |
| * | Don't call tablegen'ed Predicate_* functions in the ARM target. | Jakob Stoklund Olesen | 2010-08-17 | 1 | -4/+1 |
| * | 80 column cleanup. | Jim Grosbach | 2010-08-17 | 1 | -27/+32 |
| * | Change ARM PKHTB and PKHBT instructions to use a shift_imm operand to avoid | Bob Wilson | 2010-08-17 | 1 | -12/+12 |
| * | Generalize a pattern for PKHTB: an SRL of 16-31 bits will guarantee | Bob Wilson | 2010-08-16 | 1 | -2/+4 |
| * | Rename sat_shift operand to shift_imm, in preparation for using it for other | Bob Wilson | 2010-08-16 | 1 | -2/+2 |
| * | T2I_rbin_irs rr variant is for disassembly only, so don't provide a pattern. | Bob Wilson | 2010-08-14 | 1 | -1/+1 |
| * | Add a Thumb2 t2RSBrr instruction for disassembly only. | Bob Wilson | 2010-08-13 | 1 | -5/+18 |
| * | Move the Thumb2 SSAT and USAT optional shift operator out of the | Bob Wilson | 2010-08-13 | 1 | -30/+8 |
| * | Really control isel of barrier instructions with cpu feature. | Evan Cheng | 2010-08-11 | 1 | -2/+2 |
| * | - Add subtarget feature -mattr=+db which determine whether an ARM cpu has the | Evan Cheng | 2010-08-11 | 1 | -10/+4 |
| * | ARM: Quote $p in an asm string. | Daniel Dunbar | 2010-08-11 | 1 | -2/+2 |
| * | CBZ and CBNZ are implemented. | Evan Cheng | 2010-08-10 | 1 | -5/+0 |
| * | Delete some unused instructions. | Evan Cheng | 2010-08-10 | 1 | -14/+0 |
| * | Use the "isCompare" machine instruction attribute instead of calling the | Bill Wendling | 2010-08-08 | 1 | -1/+2 |
| * | Move newlines before inline jumptables from the asm strings in .td files to | Bob Wilson | 2010-07-31 | 1 | -3/+3 |
| * | Many Thumb2 instructions can reference the full ARM register set (i.e., | Jim Grosbach | 2010-07-30 | 1 | -284/+293 |
| * | Add builtins for ssat/usat, similar to RealView's __ssat and __usat intrinsics. | Nate Begeman | 2010-07-29 | 1 | -0/+3 |
| * | Add intrinsics __builtin_arm_qadd & __builtin_arm_qsub to allow access to the... | Nate Begeman | 2010-07-29 | 1 | -4/+7 |
| * | Remove incorrect substitution pattern for UXTB16. It wrongly assumed the inpu... | Jim Grosbach | 2010-07-28 | 1 | -2/+6 |
| * | Using BIC for immediates needs an extra bump for its complexity to get | Jim Grosbach | 2010-07-20 | 1 | -0/+1 |
| * | Add basic support to code-gen the ARM/Thumb2 bit-field insert (BFI) instruction | Jim Grosbach | 2010-07-16 | 1 | -4/+6 |
| * | Improve 64-subtraction of immediates when parts of the immediate can fit | Jim Grosbach | 2010-07-14 | 1 | -6/+29 |
| * | Add missing address register update to t2LDM_RET instruction. | Bob Wilson | 2010-07-14 | 1 | -1/+1 |
| * | PR7503: uxtb16 is not available for ARMv7-M. Patch by Brian G. Lucas. | Evan Cheng | 2010-06-29 | 1 | -2/+2 |
| * | Always allow Thumb-2 SXTB, SXTH, UXTB, and UXTH. Fixes PR7324. | Eli Friedman | 2010-06-24 | 1 | -11/+9 |
| * | LEApcrelJT shouldn't be marked as neverHasSideEffects, as we don't want it | Jim Grosbach | 2010-06-21 | 1 | -1/+1 |
| * | Allow ARM if-converter to be run after post allocation scheduling. | Evan Cheng | 2010-06-18 | 1 | -0/+1 |
| * | Clean up 80 column violations. No functional change. | Jim Grosbach | 2010-06-02 | 1 | -1/+2 |
| * | Cosmetic cleanup. No functional change. | Jim Grosbach | 2010-05-28 | 1 | -12/+12 |
| * | make sure accesses to set up the jmpbuf don't get moved after it by the sched... | Jim Grosbach | 2010-05-28 | 1 | -2/+3 |
| * | Update the saved stack pointer in the sjlj function context following either | Jim Grosbach | 2010-05-27 | 1 | -5/+3 |
| * | fix off by 1 (insn) error in eh.sjlj.setjmp thumb code sequence. | Jim Grosbach | 2010-05-26 | 1 | -2/+2 |
| * | Allow t2MOVsrl_flag and t2MOVsra_flag instructions to be predicated. | Bob Wilson | 2010-05-25 | 1 | -6/+6 |
| * | Fix up instruction classes for Thumb2 RSB instructions to be consistent with | Bob Wilson | 2010-05-25 | 1 | -15/+15 |
| * | Allow Thumb2 MVN instructions to set condition codes. The immediate operand | Bob Wilson | 2010-05-24 | 1 | -5/+5 |
| * | Thumb2 RSBS instructions were being printed without the 'S' suffix. | Bob Wilson | 2010-05-24 | 1 | -6/+4 |
| * | t2LEApcrel and tLEApcrel are re-materializable. This makes it possible to hoi... | Evan Cheng | 2010-05-19 | 1 | -0/+1 |
| * | Mark pattern-less mayLoad / mayStore instructions neverHasSideEffects. These ... | Evan Cheng | 2010-05-19 | 1 | -9/+9 |
| * | Mark a few more pattern-less instructions with neverHasSideEffects. This is e... | Evan Cheng | 2010-05-19 | 1 | -0/+4 |
| * | Chris said that the comment char should be escaped. Fix all the occurences of... | Anton Korobeynikov | 2010-05-16 | 1 | -8/+8 |
| * | Cleanup of ARMv7M support. Move hardware divide and Thumb2 extract/pack | Jim Grosbach | 2010-05-05 | 1 | -14/+14 |
| * | Add initial support for ARMv7M subtarget and cortex-m3 cpu. Patch by | Jim Grosbach | 2010-05-05 | 1 | -15/+31 |
| * | Provide versions of the ARM eh_sjlj_setjmp instructions for non-VFP subtargets | Bob Wilson | 2010-04-09 | 1 | -1/+17 |
| * | Remove the writeback flag from ARM's address mode 4. Now that we have separate | Bob Wilson | 2010-03-16 | 1 | -2/+2 |
| * | Change ARM ld/st multiple instructions to have variant instructions for | Bob Wilson | 2010-03-13 | 1 | -15/+42 |
| * | Set the (Format)F filed of t2Int_MemBarrierV7 & t2Int_SyncBarrierV7 to ThumbFrm, | Johnny Chen | 2010-03-11 | 1 | -2/+2 |
| * | Added Thumb2 LDRD/STRD pre/post variants for disassembly only. | Johnny Chen | 2010-03-11 | 1 | -2/+23 |
| * | Factored out the disassembly printing of CPS option, MSR mask, and Negative Zero | Johnny Chen | 2010-03-10 | 1 | -12/+14 |
| * | MSR (Move to Special Register from ARM core register) requires a mask to specify | Johnny Chen | 2010-03-09 | 1 | -4/+4 |
