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path: root/lib/Target/ARM/ARMInstrVFP.td
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* Add parameter to pattern classes to enable an itinerary to be specified for i...David Goodwin2009-08-061-57/+57
* Add NEON single-precision FP support for fabs and fneg.David Goodwin2009-08-041-6/+6
* Match common pattern for FNMAC. Add NEON SP support.David Goodwin2009-08-041-0/+5
* Initial support for single-precision FP using NEON. Added "neonfp" attribute ...David Goodwin2009-08-041-15/+15
* Model fpscr to prevent fcmped / fcmpezs etc from being deleted.Evan Cheng2009-07-201-1/+5
* Predicate VFP instructions on HasVFP2 instead of IsARM. This allows VFP instr...David Goodwin2009-07-101-4/+4
* Mark some pattern-less instructions as neverHasSideEffects.Evan Cheng2009-06-121-0/+2
* Fix a 80 col. violation.Evan Cheng2008-12-111-1/+2
* Rename isSimpleLoad to canFoldAsLoad, to better reflect its meaning.Dan Gohman2008-12-031-2/+2
* Fix fuitos encoding.Evan Cheng2008-11-151-8/+4
* fsub{d|s} encoding bugs.Evan Cheng2008-11-131-2/+6
* Consolidate formats; fix FCMPED etc. encodings.Evan Cheng2008-11-121-10/+5
* Fix VFP conversion instruction encodings.Evan Cheng2008-11-121-12/+12
* Fix encoding of single-precision VFP registers.Evan Cheng2008-11-121-1/+1
* Fix FMDRR encoding.Evan Cheng2008-11-111-9/+9
* Encode VFP load / store instructions.Evan Cheng2008-11-111-9/+24
* Encode VFP conversion instructions.Evan Cheng2008-11-111-28/+57
* Encode VFP arithmetic instructions.Evan Cheng2008-11-111-102/+72
* Remove opcode from instruction TS flags; add MOVCC support; fix addrmode3 enc...Evan Cheng2008-11-061-8/+8
* udpate header comment: s/VP/VFP/Jim Grosbach2008-09-111-1/+1
* Replace all target specific implicit def instructions with a target independe...Evan Cheng2008-03-151-9/+0
* rename SDTRet -> SDTNone.Chris Lattner2008-01-151-1/+1
* get def use info more correct.Chris Lattner2008-01-101-0/+2
* Only mark instructions that load a single value without extension as isSimple...Evan Cheng2008-01-071-2/+0
* rename isLoad -> isSimpleLoad due to evan's desire to have such a predicate.Chris Lattner2008-01-061-4/+4
* rename isStore -> mayStore to more accurately reflect what it captures.Chris Lattner2008-01-061-2/+2
* remove explicit isStore flags that are now inferrable.Chris Lattner2008-01-061-2/+0
* Remove attribution from file headers, per discussion on llvmdev.Chris Lattner2007-12-291-2/+2
* Implicit def instructions, e.g. X86::IMPLICIT_DEF_GR32, are always re-materia...Evan Cheng2007-12-121-0/+2
* Remove (somewhat confusing) Imp<> helper, use let Defs = [], Uses = [] instead.Evan Cheng2007-09-111-1/+2
* Initial JIT support for ARM by Raul Fernandes Herbster.Evan Cheng2007-08-071-8/+14
* Change instruction description to split OperandList into OutOperandList andEvan Cheng2007-07-191-75/+79
* Remove clobbersPred. Add an OptionalDefOperand to instructions which have the...Evan Cheng2007-07-101-1/+0
* No need for ccop anymore.Evan Cheng2007-07-061-8/+8
* Each ARM use predicate operand is now made up of two components. The new comp...Evan Cheng2007-07-051-17/+15
* Mark these instructions clobbersPred. They modify the condition code register.Evan Cheng2007-06-061-1/+1
* For VFP2 fldm, fstm instructions, the condition code is printed after the add...Evan Cheng2007-05-291-4/+4
* Add PredicateOperand to all ARM instructions that have the condition field.Evan Cheng2007-05-151-71/+95
* Switch BCC, MOVCCr, etc. to PredicateOperand.Evan Cheng2007-05-081-4/+4
* This is no longer needed after enabling the DAG combiner xform.Evan Cheng2007-05-071-5/+0
* Evan's patch to avoid FPreg->intreg copy for cvt; store to memDale Johannesen2007-05-031-0/+5
* match a reassociated form of fnmul. This implements CodeGen/ARM/fnmul.llChris Lattner2007-05-031-2/+8
* ARM backend contribution from Apple.Evan Cheng2007-01-191-0/+359