| Commit message (Expand) | Author | Age | Files | Lines |
* | Swift: Only build vldm/vstm with q register aligned register lists | Arnold Schwaighofer | 2013-09-04 | 1 | -1/+4 |
* | Use SmallVectorImpl& instead of SmallVector to avoid repeating small vector s... | Craig Topper | 2013-07-14 | 1 | -7/+7 |
* | Simplify code. | Craig Topper | 2013-07-10 | 1 | -6/+2 |
* | Use SmallVectorImpl::iterator/const_iterator instead of SmallVector to avoid ... | Craig Topper | 2013-07-04 | 1 | -4/+4 |
* | ARM: Remove a (false) dependency on the memoryoperand's value as we do not use | Quentin Colombet | 2013-06-20 | 1 | -1/+2 |
* | Fix for PR14824, An ARM Load/Store Optimization bug | Hao Liu | 2013-04-18 | 1 | -1/+17 |
* | Reverting 178851 as it broke buildbots | Renato Golin | 2013-04-05 | 1 | -161/+10 |
* | Buildbot fix for r178851: mistake was in wrong TargetRegisterInfo::getRegClas... | Stepan Dyatkovskiy | 2013-04-05 | 1 | -1/+1 |
* | Fix for PR14824: "Optimization arm_ldst_opt inserts newly generated instructi... | Stepan Dyatkovskiy | 2013-04-05 | 1 | -10/+161 |
* | [arm load/store optimizer] When trying to merge a base update load/store, make | Chad Rosier | 2013-03-25 | 1 | -1/+1 |
* | Radar numbers don't belong in source code. | Evan Cheng | 2013-02-21 | 1 | -1/+0 |
* | Move all of the header files which are involved in modelling the LLVM IR | Chandler Carruth | 2013-01-02 | 1 | -3/+3 |
* | Add an MF argument to MI::copyImplicitOps(). | Jakob Stoklund Olesen | 2012-12-20 | 1 | -1/+1 |
* | Use the new script to sort the includes of every file under lib. | Chandler Carruth | 2012-12-03 | 1 | -11/+11 |
* | Move TargetData to DataLayout. | Micah Villmow | 2012-10-08 | 1 | -3/+3 |
* | Remove getARMRegisterNumbering and replace with calls into | Eric Christopher | 2012-08-09 | 1 | -4/+2 |
* | Add an MF argument to TRI::getPointerRegClass() and TII::getRegClass(). | Jakob Stoklund Olesen | 2012-05-07 | 1 | -1/+1 |
* | ARM: Nuke remnant bogus code. | Jim Grosbach | 2012-04-24 | 1 | -2/+0 |
* | Convert more uses of XXXRegisterClass to &XXXRegClass. No functional change s... | Craig Topper | 2012-04-20 | 1 | -1/+1 |
* | ARM LDR/LDRT has the same encoding collision as STR/STRT. | Jim Grosbach | 2012-04-10 | 1 | -8/+7 |
* | ARM: Don't form a t2LDRi8 or t2STRi8 with an offset of zero. | Jim Grosbach | 2012-04-05 | 1 | -0/+8 |
* | Don't kill the base register when expanding strd. | Jakob Stoklund Olesen | 2012-03-28 | 1 | -0/+4 |
* | Preserve implicit defs in ARMLoadStoreOptimizer. | Jakob Stoklund Olesen | 2012-03-28 | 1 | -3/+20 |
* | Revert r153516: "Invalidate liveness in Thumb2ITBlockPass." | Jakob Stoklund Olesen | 2012-03-28 | 1 | -4/+0 |
* | ARMLoadStoreOptimizer invalidates register liveness. | Jakob Stoklund Olesen | 2012-03-27 | 1 | -0/+4 |
* | Remove unnecessary llvm:: qualifications | Craig Topper | 2012-03-27 | 1 | -8/+8 |
* | Prune includes and replace uses of ARMRegisterInfo.h with ARMBaeRegisterInfo.h | Craig Topper | 2012-03-26 | 1 | -1/+1 |
* | Emacs-tag and some comment fix for all ARM, CellSPU, Hexagon, MBlaze, MSP430,... | Jia Liu | 2012-02-18 | 1 | -1/+1 |
* | Do not fold ADD / SUB into load / store (to form pre-indexed, post-indexed | Evan Cheng | 2012-02-07 | 1 | -24/+58 |
* | More dead code removal (using -Wunreachable-code) | David Blaikie | 2012-01-20 | 1 | -24/+0 |
* | ARM Ld/St Optimizer fix. | Andrew Trick | 2012-01-11 | 1 | -3/+4 |
* | Add bundle aware API for querying instruction properties and switch the code | Evan Cheng | 2011-12-07 | 1 | -7/+5 |
* | ARMLoadStoreOptimizer.cpp: Fix MSVC(Debug) build. | NAKAMURA Takumi | 2011-11-25 | 1 | -0/+1 |
* | Preserve MachineMemOperands in ARMLoadStoreOptimizer. | Andrew Trick | 2011-11-11 | 1 | -0/+22 |
* | Hide cpu name checking in ARMSubtarget. | Evan Cheng | 2011-11-09 | 1 | -1/+1 |
* | Add workaround for Cortex-M3 errata 602117 by replacing ldrd x, y, [x] with l... | Evan Cheng | 2011-11-08 | 1 | -3/+9 |
* | Apply the same fix for the change in LDR_PRE_IMM/LDRB_PRE_IMM operand encodin... | Owen Anderson | 2011-08-29 | 1 | -1/+2 |
* | Update the load-store optimizer for changes to the operands on LDR_PRE_IMM an... | Owen Anderson | 2011-08-29 | 1 | -4/+10 |
* | invalid-LDR_PRE-arm.txt was already passing, but for the wrong reasons. We w... | Owen Anderson | 2011-08-26 | 1 | -1/+1 |
* | ARM STR_POST_IMM offset encoding fix in load/store optimizer. | Jim Grosbach | 2011-08-12 | 1 | -13/+10 |
* | ARM refactor indexed store instructions. | Jim Grosbach | 2011-08-05 | 1 | -2/+8 |
* | Split am2offset into register addend and immediate addend forms, necessary fo... | Owen Anderson | 2011-07-26 | 1 | -3/+3 |
* | Sink ARMMCExpr and ARMAddressingModes into MC layer. First step to separate A... | Evan Cheng | 2011-07-20 | 1 | -1/+2 |
* | Remove redundant Thumb2 ADD/SUB SP instruction definitions. | Jim Grosbach | 2011-06-29 | 1 | -10/+2 |
* | - Rename TargetInstrDesc, TargetOperandInfo to MCInstrDesc and MCOperandInfo and | Evan Cheng | 2011-06-28 | 1 | -11/+11 |
* | More refactoring. Move getRegClass from TargetOperandInfo to TargetInstrInfo. | Evan Cheng | 2011-06-27 | 1 | -1/+1 |
* | Clean up comment a bit. | Eric Christopher | 2011-05-25 | 1 | -2/+2 |
* | Fix more of PR8825. Now all of CodeGen/ARM passes with VerifyCoalescing turne... | Cameron Zwarich | 2011-05-18 | 1 | -4/+7 |
* | use the MachineInstrBuilder operator-> to simplify some code. | Chris Lattner | 2011-04-29 | 1 | -1/+1 |
* | Fix a ton of comment typos found by codespell. Patch by | Chris Lattner | 2011-04-15 | 1 | -4/+4 |