| Commit message (Expand) | Author | Age | Files | Lines |
|---|
| * | Don't cache the instruction and register info from the TargetMachine, because | Bill Wendling | 2013-06-07 | 1 | -3/+2 |
| * | Reorder includes to match coding standards. Fix an issue or two exposed by that. | Craig Topper | 2012-03-17 | 1 | -1/+1 |
| * | Emacs-tag and some comment fix for all ARM, CellSPU, Hexagon, MBlaze, MSP430,... | Jia Liu | 2012-02-18 | 1 | -1/+1 |
| * | Unweaken vtables as per http://llvm.org/docs/CodingStandards.html#ll_virtual_... | David Blaikie | 2011-12-20 | 1 | -0/+2 |
| * | Trim a few unneeded includes. | Jim Grosbach | 2011-04-18 | 1 | -18/+0 |
| * | Rename TargetFrameInfo into TargetFrameLowering. Also, put couple of FIXMEs a... | Anton Korobeynikov | 2011-01-10 | 1 | -1/+0 |
| * | Generalize opcode selection in ARMBaseRegisterInfo. | David Goodwin | 2009-07-08 | 1 | -0/+1 |
| * | Push methods into base class in preparation for sharing. | David Goodwin | 2009-07-08 | 1 | -533/+1 |
| * | Start converting to new error handling API. | Torok Edwin | 2009-07-08 | 1 | -2/+2 |
| * | Start breaking out common base functionality for register info. | David Goodwin | 2009-07-08 | 1 | -830/+0 |
| * | Fix a comment typo. | Bob Wilson | 2009-07-01 | 1 | -1/+1 |
| * | Simplify a bit | Anton Korobeynikov | 2009-06-27 | 1 | -37/+23 |
| * | ARM refactoring. Step 2: split RegisterInfo | Anton Korobeynikov | 2009-06-27 | 1 | -615/+144 |
| * | For Darwin on ARMv6 and newer, make register r9 available for use as a | Bob Wilson | 2009-06-22 | 1 | -2/+31 |
| * | hasFP should return true if frame address is taken. | Evan Cheng | 2009-06-22 | 1 | -1/+3 |
| * | Remove UseThumbBacktraces. Just check if subtarget is darwin. | Evan Cheng | 2009-06-18 | 1 | -4/+3 |
| * | - Update register allocation hint after coalescing. This is done by the targe... | Evan Cheng | 2009-06-18 | 1 | -63/+95 |
| * | On Darwin, frame pointer r7 is never available. | Evan Cheng | 2009-06-15 | 1 | -2/+2 |
| * | Part 1. | Evan Cheng | 2009-06-15 | 1 | -4/+301 |
| * | Untabification. | Bill Wendling | 2009-05-30 | 1 | -1/+1 |
| * | Follow up on new support for memory operands in ARM inline assembly. | Bob Wilson | 2009-05-19 | 1 | -0/+4 |
| * | Change MachineInstrBuilder::addReg() to take a flag instead of a list of | Bill Wendling | 2009-05-13 | 1 | -15/+15 |
| * | PR2985 / <rdar://problem/6584986> | Jim Grosbach | 2009-04-07 | 1 | -9/+36 |
| * | Fix some significant problems with constant pools that resulted in unnecessar... | Evan Cheng | 2009-03-13 | 1 | -1/+1 |
| * | Propagate debug loc info through prologue/epilogue. | Bill Wendling | 2009-02-23 | 1 | -4/+8 |
| * | and one more file | Dale Johannesen | 2009-02-13 | 1 | -64/+92 |
| * | Move getPointerRegClass from TargetInstrInfo to TargetRegisterInfo. | Evan Cheng | 2009-02-06 | 1 | -0/+4 |
| * | Preliminary ARM debug support based on patch by Mikael of FlexyCore. | Evan Cheng | 2008-12-10 | 1 | -2/+1 |
| * | Add a sanity-check to tablegen to catch the case where isSimpleLoad | Dan Gohman | 2008-12-03 | 1 | -1/+1 |
| * | Fix encoding of single-precision VFP registers. | Evan Cheng | 2008-11-12 | 1 | -0/+74 |
| * | Switch the MachineOperand accessors back to the short names like | Dan Gohman | 2008-10-03 | 1 | -4/+4 |
| * | Re-apply 56683 with fixes. | Evan Cheng | 2008-09-27 | 1 | -1/+2 |
| * | Temporarily reverting r56683. This is causing a failure during the build of l... | Bill Wendling | 2008-09-26 | 1 | -3/+1 |
| * | Fix @llvm.frameaddress codegen. FP elimination optimization should be disable... | Evan Cheng | 2008-09-26 | 1 | -1/+3 |
| * | Infrastructure for getting the machine code size of a function and an instruc... | Nicolas Geoffray | 2008-04-16 | 1 | -1/+1 |
| * | Move reMaterialize() from TargetRegisterInfo to TargetInstrInfo. | Evan Cheng | 2008-03-31 | 1 | -30/+12 |
| * | Spiller now remove unused spill slots. | Evan Cheng | 2008-02-27 | 1 | -0/+2 |
| * | Remove bunch of gcc 4.3-related warnings from Target | Anton Korobeynikov | 2008-02-20 | 1 | -1/+2 |
| * | Rename MRegisterInfo to TargetRegisterInfo. | Dan Gohman | 2008-02-10 | 1 | -1/+1 |
| * | rename MachineInstr::setInstrDescriptor -> setDesc | Chris Lattner | 2008-01-11 | 1 | -7/+7 |
| * | rename TargetInstrDescriptor -> TargetInstrDesc. | Chris Lattner | 2008-01-07 | 1 | -2/+2 |
| * | Rename MachineInstr::getInstrDescriptor -> getDesc(), which reflects | Chris Lattner | 2008-01-07 | 1 | -2/+2 |
| * | Move even more functionality from MRegisterInfo into TargetInstrInfo. | Owen Anderson | 2008-01-07 | 1 | -151/+45 |
| * | rename isLoad -> isSimpleLoad due to evan's desire to have such a predicate. | Chris Lattner | 2008-01-06 | 1 | -2/+2 |
| * | rename isStore -> mayStore to more accurately reflect what it captures. | Chris Lattner | 2008-01-06 | 1 | -1/+1 |
| * | Move some more functionality from MRegisterInfo to TargetInstrInfo. | Owen Anderson | 2008-01-04 | 1 | -44/+0 |
| * | Move some more instruction creation methods from RegisterInfo into InstrInfo. | Owen Anderson | 2008-01-01 | 1 | -128/+0 |
| * | Move copyRegToReg from MRegisterInfo to TargetInstrInfo. This is part of the | Owen Anderson | 2007-12-31 | 1 | -28/+0 |
| * | Rename SSARegMap -> MachineRegisterInfo in keeping with the idea | Chris Lattner | 2007-12-31 | 1 | -11/+12 |
| * | Add new shorter predicates for testing machine operands for various types: | Chris Lattner | 2007-12-30 | 1 | -2/+2 |
