| Commit message (Expand) | Author | Age | Files | Lines |
|---|
| * | ARM assembly parsing of MRS instruction. | Jim Grosbach | 2011-07-19 | 1 | -2/+4 |
| * | Add support for the 'h' constraint. | Eric Christopher | 2011-06-30 | 1 | -0/+3 |
| * | Switch ARM to using AltOrders instead of MethodBodies. | Jakob Stoklund Olesen | 2011-06-18 | 1 | -223/+26 |
| * | Use set operations instead of plain lists to enumerate register classes. | Jakob Stoklund Olesen | 2011-06-15 | 1 | -36/+17 |
| * | Flag unallocatable register classes instead of giving them empty | Jakob Stoklund Olesen | 2011-06-02 | 1 | -1/+3 |
| * | Eliminate the ARM sub-register indexes that are not needed by the sources. | Jakob Stoklund Olesen | 2011-05-07 | 1 | -33/+6 |
| * | As per ARM docs, register Dx is described as DW_OP_regx(256+x) in DWARF. | Devang Patel | 2011-04-21 | 1 | -24/+32 |
| * | Prefer cheap registers for busy live ranges. | Jakob Stoklund Olesen | 2011-04-20 | 1 | -0/+3 |
| * | Sorry, several patches in one. | Evan Cheng | 2011-01-20 | 1 | -1/+1 |
| * | Create two new generic classes to represent the following VMRS/VMSR variations: | Bruno Cardoso Lopes | 2011-01-18 | 1 | -0/+4 |
| * | PR8359: The ARM backend may end up allocating registers D16 to D31 when | Bob Wilson | 2010-10-12 | 1 | -3/+3 |
| * | Change register allocation order for ARM VFP and NEON registers to put the | Bob Wilson | 2010-10-08 | 1 | -6/+72 |
| * | Now that register allocation properly considers reserved regs, simplify the | Jim Grosbach | 2010-09-02 | 1 | -154/+18 |
| * | trivial cleanup | Jim Grosbach | 2010-09-02 | 1 | -4/+2 |
| * | Simplify the tGPR register class now that the register allocators know not | Jim Grosbach | 2010-09-01 | 1 | -26/+1 |
| * | fix emacs language spec's, patch by Edmund Grimley-Evans! | Chris Lattner | 2010-08-17 | 1 | -1/+1 |
| * | Re-apply r110655 with fixes. Epilogue must restore sp from fp if the function... | Evan Cheng | 2010-08-10 | 1 | -11/+5 |
| * | Revert r110655, "Fix ARM hasFP() semantics. It should return true whenever FP | Daniel Dunbar | 2010-08-10 | 1 | -5/+11 |
| * | Fix ARM hasFP() semantics. It should return true whenever FP register is | Evan Cheng | 2010-08-10 | 1 | -11/+5 |
| * | Many Thumb2 instructions can reference the full ARM register set (i.e., | Jim Grosbach | 2010-07-30 | 1 | -0/+109 |
| * | Clean up a comment. | Bob Wilson | 2010-07-08 | 1 | -5/+5 |
| * | Fix PR 7433. Silly typo in non-Darwin ARM tail call | Dale Johannesen | 2010-06-21 | 1 | -16/+6 |
| * | Allow ARM if-converter to be run after post allocation scheduling. | Evan Cheng | 2010-06-18 | 1 | -4/+3 |
| * | Next round of tail call changes. Register used in a tail | Dale Johannesen | 2010-06-15 | 1 | -0/+77 |
| * | Clean up 80 column violations. No functional change. | Jim Grosbach | 2010-06-02 | 1 | -1/+2 |
| * | Give SubRegIndex names to all ARM subregisters. This will be required by | Jakob Stoklund Olesen | 2010-05-26 | 1 | -14/+36 |
| * | Replace the SubRegSet tablegen class with a less error-prone mechanism. | Jakob Stoklund Olesen | 2010-05-26 | 1 | -99/+20 |
| * | Revert "Replace the SubRegSet tablegen class with a less error-prone mechanism." | Jakob Stoklund Olesen | 2010-05-26 | 1 | -20/+99 |
| * | Replace the SubRegSet tablegen class with a less error-prone mechanism. | Jakob Stoklund Olesen | 2010-05-26 | 1 | -99/+20 |
| * | Remove NumberHack entirely. | Jakob Stoklund Olesen | 2010-05-25 | 1 | -21/+21 |
| * | Switch SubRegSet to using symbolic SubRegIndices | Jakob Stoklund Olesen | 2010-05-24 | 1 | -77/+77 |
| * | Lose the dummies | Jakob Stoklund Olesen | 2010-05-24 | 1 | -22/+0 |
| * | Replace the tablegen RegisterClass field SubRegClassList with an alist-like data | Jakob Stoklund Olesen | 2010-05-24 | 1 | -47/+42 |
| * | Fix a few places that depended on the numeric value of subreg indices. | Jakob Stoklund Olesen | 2010-05-24 | 1 | -0/+1 |
| * | Switch ARMRegisterInfo.td to use SubRegIndex and eliminate the parallel enums | Jakob Stoklund Olesen | 2010-05-24 | 1 | -23/+23 |
| * | Teach two-address pass to do some coalescing while eliminating REG_SEQUENCE | Evan Cheng | 2010-05-14 | 1 | -0/+11 |
| * | Added a QQQQ register file to model 4-consecutive Q registers. | Evan Cheng | 2010-05-14 | 1 | -17/+87 |
| * | Add comment about the pseudo registers QQ, each of which is a pair of Q regis... | Evan Cheng | 2010-05-13 | 1 | -0/+5 |
| * | Re-apply 103156 and 103157. 103156 didn't break anything. 10315 exposed a coa... | Evan Cheng | 2010-05-06 | 1 | -0/+69 |
| * | Revert r103156 since it was breaking the build bots. | Eric Christopher | 2010-05-06 | 1 | -69/+0 |
| * | Adding pseudo 256-bit registers QQ0 . . . QQ7 to represent pairs of Q registe... | Evan Cheng | 2010-05-06 | 1 | -0/+69 |
| * | Make it SP, LR, PC for GPR Register Class instead of LR, SP, PC. | Johnny Chen | 2010-01-25 | 1 | -1/+1 |
| * | Fixed the order of GPR RegisterClass regs to be: ..., R10, R11, R12, ... | Johnny Chen | 2010-01-25 | 1 | -1/+1 |
| * | Remove the JustSP single-register regclass. | Jakob Stoklund Olesen | 2010-01-13 | 1 | -13/+0 |
| * | Add a SPR register class to the ARM target. | Jakob Stoklund Olesen | 2009-12-22 | 1 | -0/+13 |
| * | Add QPR_8 as a superreg class of SPR_8 and DPR_8. | Evan Cheng | 2009-11-03 | 1 | -0/+7 |
| * | Do not infer the target type for COPY_TO_REGCLASS from dest regclass, this wo... | Anton Korobeynikov | 2009-11-02 | 1 | -2/+2 |
| * | Restrict Thumb1 register allocation to low registers, even for instructions that | Jim Grosbach | 2009-10-24 | 1 | -0/+16 |
| * | FIXME no longer applies. R12 and R3 are available for allocation | Jim Grosbach | 2009-10-23 | 1 | -3/+0 |
| * | Enable allocation of R3 in Thumb1 | Jim Grosbach | 2009-10-19 | 1 | -4/+1 |
