| Commit message (Expand) | Author | Age | Files | Lines |
|---|
| * | More ARM scheduling itinerary fixes. | Evan Cheng | 2010-10-11 | 1 | -0/+3 |
| * | Proper VST scheduling itineraries. | Evan Cheng | 2010-10-11 | 1 | -1/+22 |
| * | Add VLD4 scheduling itineraries. | Evan Cheng | 2010-10-09 | 1 | -0/+3 |
| * | Finish vld3 and vld4. | Evan Cheng | 2010-10-09 | 1 | -0/+3 |
| * | Correct some load / store instruction itinerary mistakes: | Evan Cheng | 2010-10-09 | 1 | -0/+12 |
| * | Model operand cycles of vldm / vstm; also fixes scheduling itineraries of vld... | Evan Cheng | 2010-10-07 | 1 | -2/+4 |
| * | - Add TargetInstrInfo::getOperandLatency() to compute operand latencies. This | Evan Cheng | 2010-10-06 | 1 | -3/+7 |
| * | NEON scheduling info fix. vmov reg, reg are single cycle instructions. | Evan Cheng | 2010-10-01 | 1 | -0/+2 |
| * | ARM instruction itinerary fixes: | Evan Cheng | 2010-09-30 | 1 | -12/+30 |
| * | Model Cortex-a9 load to SUB, RSB, ADD, ADC, SBC, RSC, CMN, MVN, or CMP | Evan Cheng | 2010-09-29 | 1 | -0/+1 |
| * | Separate itinerary classes for mvn from mov; for tst / teq from cmp / cmn. | Evan Cheng | 2010-09-29 | 1 | -1/+9 |
| * | Assign bitwise binary instructions different itinerary classes from ALU instr... | Evan Cheng | 2010-09-29 | 1 | -0/+5 |
| * | Add support to model pipeline bypass / forwarding. | Evan Cheng | 2010-09-28 | 1 | -1/+1 |
| * | Remove a unused instruction itinerary class. | Evan Cheng | 2010-09-25 | 1 | -1/+0 |
| * | Fix zero and sign extension instructions scheduling itineraries. | Evan Cheng | 2010-09-25 | 1 | -0/+2 |
| * | More pseudo instruction scheduling itinerary fixes. | Evan Cheng | 2010-09-24 | 1 | -0/+1 |
| * | Fix scheduling itinerary for pseudo mov immediate instructions which expand i... | Evan Cheng | 2010-09-24 | 1 | -0/+1 |
| * | For each instruction itinerary class, specify the number of micro-ops each | Evan Cheng | 2010-09-09 | 1 | -5/+5 |
| * | Fix LDM_RET schedule itinery. | Evan Cheng | 2010-09-08 | 1 | -0/+1 |
| * | Make processor FUs unique for given itinerary. This extends the limit of 32 | Anton Korobeynikov | 2010-04-18 | 1 | -15/+1 |
| * | Split A8/A9 itins - they already were too big. | Anton Korobeynikov | 2010-04-07 | 1 | -1/+2 |
| * | Fix itins for VABA | Anton Korobeynikov | 2010-04-07 | 1 | -0/+2 |
| * | VHADD differs from VHSUB at least on A9 - the former reads both operands in t... | Anton Korobeynikov | 2010-04-07 | 1 | -0/+2 |
| * | Define new itin classes for ARM <-> VFP reg moves to distinguish from NEON op... | Anton Korobeynikov | 2010-04-07 | 1 | -0/+4 |
| * | Add new itin classes for FP16 <-> FP32 conversions and make uise of them for A9. | Anton Korobeynikov | 2010-04-07 | 1 | -0/+2 |
| * | Make use of new reserved/required scheduling stuff: introduce VFP and NEON lo... | Anton Korobeynikov | 2010-04-07 | 1 | -0/+2 |
| * | Finish scheduling itineraries for NEON. | David Goodwin | 2009-09-25 | 1 | -4/+30 |
| * | Make the end-of-itinerary mark explicit. Some cleanup. | David Goodwin | 2009-09-24 | 1 | -84/+1 |
| * | Checkpoint NEON scheduling itineraries. | David Goodwin | 2009-09-23 | 1 | -1/+31 |
| * | Add Cortex-A8 VFP model. | David Goodwin | 2009-09-21 | 1 | -10/+68 |
| * | Update Cortex-A8 instruction itineraries for integer instructions. | David Goodwin | 2009-08-19 | 1 | -17/+91 |
| * | Turn on if-conversion for thumb2. | Evan Cheng | 2009-08-15 | 1 | -2/+4 |
| * | Finalize itineraries for cortex-a8 integer multiply | David Goodwin | 2009-08-13 | 1 | -2/+6 |
| * | Allow a zero cycle stage to reserve/require a FU without advancing the cycle ... | David Goodwin | 2009-08-11 | 1 | -5/+10 |
| * | Checkpoint scheduling itinerary changes. | David Goodwin | 2009-08-10 | 1 | -6/+14 |
| * | Add fake v7 itineraries for now. | Evan Cheng | 2009-07-21 | 1 | -0/+1 |
| * | Latency information for ARM v6. It's rough and not yet hooked up. Right now ... | Evan Cheng | 2009-06-19 | 1 | -0/+35 |
