| Commit message (Expand) | Author | Age | Files | Lines |
|---|
| * | Added MispredictPenalty to SchedMachineModel. | Andrew Trick | 2012-08-08 | 1 | -0/+1 |
| * | I'm introducing a new machine model to simultaneously allow simple | Andrew Trick | 2012-07-07 | 1 | -5/+16 |
| * | Reapply "Make NumMicroOps a variable in the subtarget's instruction itinerary." | Andrew Trick | 2012-07-02 | 1 | -14/+20 |
| * | Revert "Make NumMicroOps a variable in the subtarget's instruction itinerary." | Andrew Trick | 2012-06-29 | 1 | -20/+14 |
| * | Make NumMicroOps a variable in the subtarget's instruction itinerary. | Andrew Trick | 2012-06-29 | 1 | -14/+20 |
| * | ARM itinerary properties. | Andrew Trick | 2012-06-05 | 1 | -1/+5 |
| * | Fix a number of problems with ARM fused multiply add/subtract instructions. | Evan Cheng | 2012-04-11 | 1 | -0/+19 |
| * | Sorry, several patches in one. | Evan Cheng | 2011-01-20 | 1 | -0/+6 |
| * | Add support for NEON VLD3-dup instructions. | Bob Wilson | 2010-11-30 | 1 | -0/+12 |
| * | Add support for NEON VLD3-dup instructions. | Bob Wilson | 2010-11-29 | 1 | -0/+12 |
| * | Fix copy-and-paste errors in VLD2-dup scheduling itineraries. | Bob Wilson | 2010-11-29 | 1 | -2/+2 |
| * | Add support for NEON VLD2-dup instructions. | Bob Wilson | 2010-11-28 | 1 | -0/+12 |
| * | Add NEON VLD1-dup instructions (load 1 element to all lanes). | Bob Wilson | 2010-11-27 | 1 | -0/+12 |
| * | Fix incorrect scheduling itineraries for NEON vld1/vst1 instructions. | Bob Wilson | 2010-11-27 | 1 | -4/+4 |
| * | Conditional moves are slightly more expensive than moves. | Evan Cheng | 2010-11-13 | 1 | -0/+2 |
| * | Fix preload instruction isel. Only v7 supports pli, and only v7 with mp exten... | Evan Cheng | 2010-11-03 | 1 | -0/+4 |
| * | Modify scheduling itineraries to correct instruction latencies (not operand | Evan Cheng | 2010-11-03 | 1 | -237/+237 |
| * | Add NEON VST1-lane instructions. Partial fix for Radar 8599955. | Bob Wilson | 2010-11-02 | 1 | -0/+12 |
| * | Add NEON VLD1-lane instructions. Partial fix for Radar 8599955. | Bob Wilson | 2010-11-01 | 1 | -0/+12 |
| * | Fix fpscr <-> GPR latency info. | Evan Cheng | 2010-10-29 | 1 | -1/+1 |
| * | putback r116983 and fix simple-fp-encoding.ll tests | Andrew Trick | 2010-10-21 | 1 | -0/+22 |
| * | Revert r116983, which is breaking all the buildbots. | Owen Anderson | 2010-10-21 | 1 | -22/+0 |
| * | Add missing scheduling itineraries for transfers between core registers and V... | Evan Cheng | 2010-10-21 | 1 | -0/+22 |
| * | More ARM scheduling itinerary fixes. | Evan Cheng | 2010-10-11 | 1 | -0/+13 |
| * | Proper VST scheduling itineraries. | Evan Cheng | 2010-10-11 | 1 | -13/+140 |
| * | Add VLD4 scheduling itineraries. | Evan Cheng | 2010-10-09 | 1 | -3/+22 |
| * | Finish vld3 and vld4. | Evan Cheng | 2010-10-09 | 1 | -7/+26 |
| * | Complete vld2 instruction itineries. | Evan Cheng | 2010-10-09 | 1 | -3/+34 |
| * | Multiply instructions are issued on pipeline 0. They do not need to reserve p... | Evan Cheng | 2010-10-09 | 1 | -10/+5 |
| * | Correct some load / store instruction itinerary mistakes: | Evan Cheng | 2010-10-09 | 1 | -219/+174 |
| * | Model operand cycles of vldm / vstm; also fixes scheduling itineraries of vld... | Evan Cheng | 2010-10-07 | 1 | -16/+20 |
| * | - Add TargetInstrInfo::getOperandLatency() to compute operand latencies. This | Evan Cheng | 2010-10-06 | 1 | -7/+37 |
| * | Fix scheduling infor for vmovn and vshrn which I broke accidentially. | Evan Cheng | 2010-10-01 | 1 | -1/+1 |
| * | Add operand cycles for vldr / vstr. | Evan Cheng | 2010-10-01 | 1 | -4/+8 |
| * | NEON scheduling info fix. vmov reg, reg are single cycle instructions. | Evan Cheng | 2010-10-01 | 1 | -0/+8 |
| * | ARM instruction itinerary fixes: | Evan Cheng | 2010-09-30 | 1 | -44/+106 |
| * | Model Cortex-a9 load to SUB, RSB, ADD, ADC, SBC, RSC, CMN, MVN, or CMP | Evan Cheng | 2010-09-29 | 1 | -0/+1 |
| * | Separate itinerary classes for mvn from mov; for tst / teq from cmp / cmn. | Evan Cheng | 2010-09-29 | 1 | -2/+14 |
| * | Assign bitwise binary instructions different itinerary classes from ALU instr... | Evan Cheng | 2010-09-29 | 1 | -0/+7 |
| * | Add support to model pipeline bypass / forwarding. | Evan Cheng | 2010-09-28 | 1 | -1/+2 |
| * | Remove a unused instruction itinerary class. | Evan Cheng | 2010-09-25 | 1 | -1/+0 |
| * | Fix zero and sign extension instructions scheduling itineraries. | Evan Cheng | 2010-09-25 | 1 | -0/+4 |
| * | More pseudo instruction scheduling itinerary fixes. | Evan Cheng | 2010-09-24 | 1 | -1/+9 |
| * | Fix scheduling itinerary for pseudo mov immediate instructions which expand i... | Evan Cheng | 2010-09-24 | 1 | -0/+2 |
| * | Fix LDM_RET schedule itinery. | Evan Cheng | 2010-09-08 | 1 | -0/+9 |
| * | minor housekeeping cleanup: 80-column, trailing whitespace, spelling, etc.. N... | Jim Grosbach | 2010-06-28 | 1 | -42/+42 |
| * | Make processor FUs unique for given itinerary. This extends the limit of 32 | Anton Korobeynikov | 2010-04-18 | 1 | -336/+344 |
| * | Split A8/A9 itins - they already were too big. | Anton Korobeynikov | 2010-04-07 | 1 | -0/+610 |
