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* Merge commit '10251753b6897adcd22cc981c0cc42f348c109de' into merge-20130807Stephen Hines2013-08-071-0/+2
|\ | | | | | | | | | | | | | | Conflicts: lib/Archive/ArchiveReader.cpp lib/Support/Unix/PathV2.inc Change-Id: I29d8c1e321a4a380b6013f00bac6a8e4b593cc4e
| * Add a Subtarget feature 'v8fp' to the ARM backend.Joey Gouly2013-06-271-0/+1
| | | | | | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185073 91177308-0d34-0410-b5e6-96231b3b80d8
| * Add a subtarget feature 'v8' to the ARM backend.Joey Gouly2013-06-261-0/+1
| | | | | | | | | | | | | | This allows for targeting the ARMv8 AArch32 variant. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@184967 91177308-0d34-0410-b5e6-96231b3b80d8
* | Merge commit '100fbdd06be7590b23c4707a98cd605bdb519498' into merge_20130612Stephen Hines2013-06-121-7/+45
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| * ARM: Add Performance Monitor Extensions featureTim Northover2013-05-231-0/+1
| | | | | | | | | | | | | | | | | | | | Performance monitors, including a basic cycle counter, are an official extension in the ARMv7 specification. This adds support for enabling and disabling them, orthogonally from CPU selection. rdar://problem/13939186 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182602 91177308-0d34-0410-b5e6-96231b3b80d8
| * Support unaligned load/store on more ARM targetsJF Bastien2013-05-171-7/+44
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch matches GCC behavior: the code used to only allow unaligned load/store on ARM for v6+ Darwin, it will now allow unaligned load/store for v6+ Darwin as well as for v7+ on Linux and NaCl. The distinction is made because v6 doesn't guarantee support (but LLVM assumes that Apple controls hardware+kernel and therefore have conformant v6 CPUs), whereas v7 does provide this guarantee (and Linux/NaCl behave sanely). The patch keeps the -arm-strict-align command line option, and adds -arm-no-strict-align. They behave similarly to GCC's -mstrict-align and -mnostrict-align. I originally encountered this discrepancy in FastIsel tests which expect unaligned load/store generation. Overall this should slightly improve performance in most cases because of reduced I$ pressure. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182175 91177308-0d34-0410-b5e6-96231b3b80d8
| * Revert "Support unaligned load/store on more ARM targets"Derek Schuff2013-05-151-17/+4
| | | | | | | | | | | | This reverts r181898. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181944 91177308-0d34-0410-b5e6-96231b3b80d8
| * Support unaligned load/store on more ARM targetsDerek Schuff2013-05-151-4/+17
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch matches GCC behavior: the code used to only allow unaligned load/store on ARM for v6+ Darwin, it will now allow unaligned load/store for v6+ Darwin as well as for v7+ on other targets. The distinction is made because v6 doesn't guarantee support (but LLVM assumes that Apple controls hardware+kernel and therefore have conformant v6 CPUs), whereas v7 does provide this guarantee (and Linux behaves sanely). Overall this should slightly improve performance in most cases because of reduced I$ pressure. Patch by JF Bastien git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181897 91177308-0d34-0410-b5e6-96231b3b80d8
* | Merge remote-tracking branch 'upstream/master' into merge-20130502Stephen Hines2013-05-021-1/+11
|\ \ | |/ | | | | | | | | | | | | Conflicts: lib/Support/Unix/Signals.inc unittests/Transforms/Utils/Cloning.cpp Change-Id: I027581a4390ec3ce4cd8d33da8b5f4c0c7d372c8
| * ARM: Make "SMC" instructions conditional on new TrustZone architecture feature.Tim Northover2013-04-101-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | These instructions aren't universally available, but depend on a specific extension to the normal ARM architecture (rather than, say, v6/v7/...) so a new feature is appropriate. This also enables the feature by default on A-class cores which usually have these extensions, to avoid breaking existing code and act as a sensible default. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179171 91177308-0d34-0410-b5e6-96231b3b80d8
| * Avoid NEON SP-FP unless unsafe-math or DarwinRenato Golin2013-03-211-1/+10
| | | | | | | | | | | | | | | | | | | | NEON is not IEEE 754 compliant, so we should avoid lowering single-precision floating point operations with NEON unless unsafe-math is turned on. The equivalent VFP instructions are IEEE 754 compliant, but in some cores they're much slower, so some archs/OSs might still request it to be on by default, such as Swift and Darwin. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177651 91177308-0d34-0410-b5e6-96231b3b80d8
* | Merge commit 'b3201c5cf1e183d840f7c99ff779d57f1549d8e5' into merge_20130226Stephen Hines2013-03-051-41/+69
|\ \ | |/ | | | | | | | | | | | | Conflicts: include/llvm/Support/ELF.h lib/Support/DeltaAlgorithm.cpp Change-Id: I24a4fbce62eb39d924efee3c687b55e1e17b30cd
| * Reinitialize the ivars in the subtarget so that they can be reset with the ↵Bill Wendling2013-02-161-39/+45
| | | | | | | | | | | | new features. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175336 91177308-0d34-0410-b5e6-96231b3b80d8
| * Temporary revert of 175320.Bill Wendling2013-02-151-45/+39
| | | | | | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175322 91177308-0d34-0410-b5e6-96231b3b80d8
| * Reinitialize the ivars in the subtarget.Bill Wendling2013-02-151-39/+45
| | | | | | | | | | | | | | | | When we're recalculating the feature set of the subtarget, we need to have the ivars in their initial state. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175320 91177308-0d34-0410-b5e6-96231b3b80d8
| * Support changing the subtarget features in ARM.Bill Wendling2013-02-151-4/+25
| | | | | | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175315 91177308-0d34-0410-b5e6-96231b3b80d8
| * Add a special ARM trap encoding for NaCl.Eli Bendersky2013-01-301-0/+1
| | | | | | | | | | | | | | | | | | | | More details in this thread: http://lists.cs.uiuc.edu/pipermail/llvm-commits/Week-of-Mon-20130128/163783.html Patch by JF Bastien git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@173943 91177308-0d34-0410-b5e6-96231b3b80d8
* | Merge remote-tracking branch 'upstream/master' into merge-llvmStephen Hines2013-01-211-2/+10
|\ \ | |/ | | | | | | | | | | | | | | | | | | | | Conflicts: lib/CodeGen/AsmPrinter/AsmPrinter.cpp lib/CodeGen/AsmPrinter/AsmPrinterInlineAsm.cpp lib/MC/MCAssembler.cpp lib/Support/Atomic.cpp lib/Support/Memory.cpp lib/Target/ARM/ARMJITInfo.cpp Change-Id: Ib339baf88df5b04870c8df1bedcfe1f877ccab8d
| * Move all of the header files which are involved in modelling the LLVM IRChandler Carruth2013-01-021-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | into their new header subdirectory: include/llvm/IR. This matches the directory structure of lib, and begins to correct a long standing point of file layout clutter in LLVM. There are still more header files to move here, but I wanted to handle them in separate commits to make tracking what files make sense at each layer easier. The only really questionable files here are the target intrinsic tablegen files. But that's a battle I'd rather not fight today. I've updated both CMake and Makefile build systems (I think, and my tests think, but I may have missed something). I've also re-sorted the includes throughout the project. I'll be committing updates to Clang, DragonEgg, and Polly momentarily. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@171366 91177308-0d34-0410-b5e6-96231b3b80d8
| * On some ARM cpus, flags setting movs with shifter operand, i.e. lsl, lsr, asr,Evan Cheng2012-12-201-0/+1
| | | | | | | | | | | | | | | | | | | | are more expensive than the non-flag setting variant. Teach thumb2 size reduction pass to avoid generating them unless we are optimizing for size. rdar://12892707 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@170728 91177308-0d34-0410-b5e6-96231b3b80d8
| * Use the new script to sort the includes of every file under lib.Chandler Carruth2012-12-031-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Sooooo many of these had incorrect or strange main module includes. I have manually inspected all of these, and fixed the main module include to be the nearest plausible thing I could find. If you own or care about any of these source files, I encourage you to take some time and check that these edits were sensible. I can't have broken anything (I strictly added headers, and reordered them, never removed), but they may not be the headers you'd really like to identify as containing the API being implemented. Many forward declarations and missing includes were added to a header files to allow them to parse cleanly when included first. The main module rule does in fact have its merits. =] git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@169131 91177308-0d34-0410-b5e6-96231b3b80d8
| * Add LLVM support for Swift.Bob Wilson2012-09-291-0/+6
| | | | | | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@164899 91177308-0d34-0410-b5e6-96231b3b80d8
| * TableGen subtarget emitter. Initialize MCSubtargetInfo with the new machine ↵Andrew Trick2012-09-181-1/+2
| | | | | | | | | | | | model. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@164092 91177308-0d34-0410-b5e6-96231b3b80d8
| * Revert r164061-r164067. Most of the new subtarget emitter.Andrew Trick2012-09-171-2/+1
| | | | | | | | | | | | | | | | I have to work out the Target/CodeGen header dependencies before putting this back. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@164072 91177308-0d34-0410-b5e6-96231b3b80d8
| * TableGen subtarget emitter. Initialize MCSubtargetInfo with the new machine ↵Andrew Trick2012-09-171-1/+2
| | | | | | | | | | | | model. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@164061 91177308-0d34-0410-b5e6-96231b3b80d8
* | Merge branch 'upstream' into merge_2Stephen Hines2012-08-231-9/+4
|\ \ | |/ | | | | | | | | | | Conflicts: lib/Target/ARM/ARMCodeEmitter.cpp Change-Id: I6702d340c733e9721499b5d85b13b96ad9c14eb5
| * Added MispredictPenalty to SchedMachineModel.Andrew Trick2012-08-081-9/+4
| | | | | | | | | | | | | | This replaces an existing subtarget hook on ARM and allows standard CodeGen passes to potentially use the property. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@161471 91177308-0d34-0410-b5e6-96231b3b80d8
* | Merge with LLVM upstream r160668 (Jul 24th 2012)Shih-wei Liao2012-08-031-21/+3
|\ \ | |/ | | | | | | | | | | | | | | | | Conflicts: include/llvm/Support/ELF.h lib/CodeGen/AsmPrinter/AsmPrinter.cpp lib/Support/Memory.cpp lib/Transforms/Instrumentation/AddressSanitizer.cpp Change-Id: Iddd658cf2eadc7165b2805b446d31af2c5c9917f
| * ARM itinerary properties.Andrew Trick2012-06-051-20/+0
| | | | | | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@157980 91177308-0d34-0410-b5e6-96231b3b80d8
| * misched: Added MultiIssueItineraries.Andrew Trick2012-06-051-3/+4
| | | | | | | | | | | | | | | | This allows a subtarget to explicitly specify the issue width and other properties without providing pipeline stage details for every instruction. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@157979 91177308-0d34-0410-b5e6-96231b3b80d8
| * Implement a bastardized ABI.Evan Cheng2012-04-271-1/+1
| | | | | | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@155686 91177308-0d34-0410-b5e6-96231b3b80d8
| * If triple is armv7 / thumbv7 and a CPU is specified, do not automatically assumeEvan Cheng2012-04-261-1/+1
| | | | | | | | | | | | | | | | | | | | | | the feature set of v7a. This comes about if the user specifies something like -arch armv7 -mcpu=cortex-m3. We shouldn't be generating instructions such as uxtab in this case. rdar://11318438 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@155601 91177308-0d34-0410-b5e6-96231b3b80d8
| * ARM: Initialize the HasRAS bit.Benjamin Kramer2012-04-221-0/+1
| | | | | | | | | | | | Found by valgrind. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@155313 91177308-0d34-0410-b5e6-96231b3b80d8
* | Merge with LLVM upstream r155090.Shih-wei Liao2012-04-241-2/+0
|\ \ | |/ | | | | | | | | | | Conflicts: lib/Support/Unix/PathV2.inc Change-Id: I7b89833849f6cbcfa958a33a971d0f7754c9cb2c
| * Clean up ARM fused multiply + add/sub support some more: rename some iselEvan Cheng2012-04-111-1/+0
| | | | | | | | | | | | | | | | | | | | | | | | predicates. Also remove NEON2 since it's not really useful and it is confusing. If NEON + VFP4 implies NEON2 but NEON2 doesn't imply NEON + VFP4, what does it really mean? rdar://10139676 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@154480 91177308-0d34-0410-b5e6-96231b3b80d8
| * Prune some includesCraig Topper2012-03-271-1/+0
| | | | | | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153502 91177308-0d34-0410-b5e6-96231b3b80d8
* | Non-static arm-reserve-r9.Shih-wei Liao2012-04-151-1/+1
|/ | | | Change-Id: I96d9a7cb594d89e0377616ad613f8201e9aa8136
* updated patch for the ARM fused multiply add/subSebastian Pop2012-03-051-1/+1
| | | | | | | | | | | In this update: - I assumed neon2 does not imply vfpv4, but neon and vfpv4 imply neon2. - I kept setting .fpu=neon-vfpv4 code attribute because that is what the assembler understands. Patch by Ana Pazos <apazos@codeaurora.org> git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152036 91177308-0d34-0410-b5e6-96231b3b80d8
* Proper support for a bastardized darwin-eabi hybird ABI.Evan Cheng2012-02-211-2/+3
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@151083 91177308-0d34-0410-b5e6-96231b3b80d8
* Emacs-tag and some comment fix for all ARM, CellSPU, Hexagon, MBlaze, ↵Jia Liu2012-02-181-1/+1
| | | | | | MSP430, PPC, PTX, Sparc, X86, XCore. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@150878 91177308-0d34-0410-b5e6-96231b3b80d8
* Add fused multiple+add instructions from VFPv4.Anton Korobeynikov2012-01-221-0/+2
| | | | | | | Patch by Ana Pazos! git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148658 91177308-0d34-0410-b5e6-96231b3b80d8
* ARM target code clean up. Check for iOS, not Darwin where it makes sense.Evan Cheng2011-12-201-2/+2
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146981 91177308-0d34-0410-b5e6-96231b3b80d8
* Remove NaClModeDavid Meyer2011-10-181-1/+0
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142338 91177308-0d34-0410-b5e6-96231b3b80d8
* Reenable tail calls for iOS 5.0 and later.Bob Wilson2011-10-071-0/+3
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141370 91177308-0d34-0410-b5e6-96231b3b80d8
* Check in a patch that has already been code reviewed by Owen that I'd ↵James Molloy2011-09-281-0/+1
| | | | | | | | | | | | | forgotten to commit. Build on previous patches to successfully distinguish between an M-series and A/R-series MSR and MRS instruction. These take different mask names and have a *slightly* different opcode format. Add decoder and disassembler tests. Improvement on the previous patch - successfully distinguish between valid v6m and v7m masks (one is a subset of the other). The patch had to be edited slightly to apply to ToT. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140696 91177308-0d34-0410-b5e6-96231b3b80d8
* Add a new MC bit for NaCl (Native Client) mode. NaCl requires that certainNick Lewycky2011-09-051-0/+1
| | | | | | | | instructions are more aligned than the CPU requires, and adds some additional directives, to follow in future patches. Patch by David Meyer! git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139125 91177308-0d34-0410-b5e6-96231b3b80d8
* Next round of MC refactoring. This patch factor MC table instantiations, MCEvan Cheng2011-07-141-2/+0
| | | | | | | registeration and creation code into XXXMCDesc libraries. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135184 91177308-0d34-0410-b5e6-96231b3b80d8
* Eliminate asm parser's dependency on TargetMachine:Evan Cheng2011-07-081-1/+2
| | | | | | | | | | | - Each target asm parser now creates its own MCSubtatgetInfo (if needed). - Changed AssemblerPredicate to take subtarget features which tablegen uses to generate asm matcher subtarget feature queries. e.g. "ModeThumb,FeatureThumb2" is translated to "(Bits & ModeThumb) != 0 && (Bits & FeatureThumb2) != 0". git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134678 91177308-0d34-0410-b5e6-96231b3b80d8
* Rename attribute 'thumb' to a more descriptive 'thumb-mode'.Evan Cheng2011-07-071-1/+1
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134626 91177308-0d34-0410-b5e6-96231b3b80d8
* Sink feature IsThumb into MC layer.Evan Cheng2011-07-071-2/+1
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134608 91177308-0d34-0410-b5e6-96231b3b80d8
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