aboutsummaryrefslogtreecommitdiffstats
path: root/lib/Target/ARM/ARMTargetMachine.cpp
Commit message (Expand)AuthorAgeFilesLines
* Remove early IT block formation. It's not used.Evan Cheng2010-07-021-8/+0
* Add missing ARM and Thumb data layout info for vector types.Bob Wilson2010-06-251-4/+8
* Oops. IT block formation pass needs to be run at any optimization level.Evan Cheng2010-06-241-4/+3
* Move ARM if-conversion before post-ra scheduling.Evan Cheng2010-06-181-15/+2
* Allow ARM if-converter to be run after post allocation scheduling.Evan Cheng2010-06-181-2/+5
* Make post-ra scheduling, anti-dep breaking, and register scavenger (conservat...Evan Cheng2010-06-161-2/+11
* Typo.Evan Cheng2010-06-091-1/+1
* Thumb2 IT blocks are fairly expensive. When there are multiple selects usingEvan Cheng2010-06-091-0/+10
* Implement a bunch more TargetSelectionDAGInfo infrastructure.Dan Gohman2010-05-111-2/+4
* Remove late ARM codegen optimization pass committed by accident.Anton Korobeynikov2010-04-071-7/+1
* Move NEON-VFP domain fixer upper, so post-RA scheduler would benefit from it.Anton Korobeynikov2010-04-071-4/+6
* Some initial version of global mergerAnton Korobeynikov2010-04-071-1/+7
* TargetRegistry: Fix create{AsmInfo,MCDisassembler} to return non-const objects.Daniel Dunbar2010-03-201-1/+1
* remove dead code.Chris Lattner2010-02-021-24/+0
* eliminate all the dead addSimpleCodeEmitter implementations.Chris Lattner2010-02-021-25/+0
* For aligned load/store instructions, it's only required to know whether aJim Grosbach2010-01-191-4/+0
* Factor the stack alignment calculations out into a target independent pass.Jim Grosbach2009-12-021-1/+1
* Detect need for autoalignment of the stack earlier to catch spills moreJim Grosbach2009-11-151-0/+4
* indicate what the native integer types for the target are.Chris Lattner2009-11-071-4/+4
* - Add pseudo instructions tLDRpci_pic and t2LDRpci_pic which does a pc-relativeEvan Cheng2009-11-061-0/+4
* Pass StringRef by value.Daniel Dunbar2009-11-061-2/+1
* Move subtarget check upper for NEON reg-reg fixup pass.Anton Korobeynikov2009-11-031-1/+2
* Turn neon reg-reg moves fixup code into separate pass. This should reduce the...Anton Korobeynikov2009-11-031-2/+5
* Revert r85346 change to control tail merging by CodeGenOpt::Level.Bob Wilson2009-10-281-1/+1
* Record CodeGen optimization level in the BranchFolding pass so that we canBob Wilson2009-10-271-1/+1
* Revert 84843. Evan, this was breaking some of the if-conversion tests.Bob Wilson2009-10-221-3/+5
* Move if-conversion before post-regalloc scheduling so the predicated instruct...Evan Cheng2009-10-221-5/+3
* Trim include.Evan Cheng2009-10-221-1/+0
* Move load / store multiple before post-alloc scheduling.Evan Cheng2009-10-021-10/+2
* Add a option which would move ld/st multiple pass before post-alloc scheduling.Evan Cheng2009-09-301-1/+16
* Pass the optimization level when constructing the ARM instruction selector.Bob Wilson2009-09-281-1/+1
* Enable pre-regalloc load / store multiple pass for Thumb2.Evan Cheng2009-09-271-6/+5
* Really remove this option.Evan Cheng2009-09-261-3/+0
* Remove a couple of unused command line options.Evan Cheng2009-09-261-7/+3
* trivial whitespace cleanupJim Grosbach2009-09-141-2/+2
* rename COFFMCAsmInfo -> MCAsmInfoCOFF, likewise for darwin.Chris Lattner2009-08-221-1/+1
* Rename TargetAsmInfo (and its subclasses) to MCAsmInfo.Chris Lattner2009-08-221-6/+6
* Turn on if-conversion for thumb2.Evan Cheng2009-08-151-6/+4
* Revert 78892 and 78895, these break generating working executables onDaniel Dunbar2009-08-131-1/+1
* fix a minor fixme. When building with SL and later tools, the ".eh" symbolsChris Lattner2009-08-131-1/+1
* Change TargetAsmInfo to be constructed via TargetRegistry from a Target+TripleChris Lattner2009-08-121-10/+16
* pass the TargetTriple down from each target ctor to theChris Lattner2009-08-111-1/+1
* Whitespace cleanup. Remove trailing whitespace.Jim Grosbach2009-08-111-1/+1
* Adding a blank line back.Evan Cheng2009-08-111-0/+1
* Enable Thumb2 instruction shrinking (32-bit to 16-bit) pass. Convert a bunch ...Evan Cheng2009-08-101-5/+1
* Add a skeleton Thumb2 instruction size reduction pass.Evan Cheng2009-08-081-1/+6
* Add a new pre-allocation pass to assign adjacent registers for Neon instructionsBob Wilson2009-08-051-0/+3
* Oops. I didn't mean to commit this piece yet.Bob Wilson2009-08-051-2/+0
* Change DAG nodes for Neon VLD2/3/4 operations to return multiple results.Bob Wilson2009-08-051-0/+2
* Enable load / store multiple pass for Thumb2. It's not using ldrd / strd yet.Evan Cheng2009-08-041-2/+3
generated by cgit v1.1 at 2024-09-10 16:41:43 +0000