| Commit message (Expand) | Author | Age | Files | Lines |
|---|
| ... | |
| * | Fix an ambiguous decoding where we failed to properly decode VMOVv2f32 and VM... | Owen Anderson | 2011-11-15 | 1 | -8/+62 |
| * | Re-apply 144430, this time with the associated isel and disassmbler bits. | Jim Grosbach | 2011-11-12 | 1 | -4/+0 |
| * | Remove the unnecessary dependency on libARMCodeGen from libARMDisassembler. | Benjamin Kramer | 2011-11-11 | 1 | -1/+1 |
| * | The rules disallowing single-register reglist operands only apply to the POP ... | Owen Anderson | 2011-11-02 | 1 | -5/+1 |
| * | Register list operands are not allowed to contain only a single register. Al... | Owen Anderson | 2011-11-02 | 1 | -1/+5 |
| * | Fix disassembly of some VST1 instructions. | Owen Anderson | 2011-11-01 | 1 | -5/+19 |
| * | ARM VST1 w/ writeback assembly parsing and encoding. | Jim Grosbach | 2011-10-31 | 1 | -12/+16 |
| * | More not-crashing NEON disassembly updates for the vld refactoring. | Owen Anderson | 2011-10-31 | 1 | -0/+4 |
| * | Reapply r143202, with a manual decoding hook for SWP. This change inadvertan... | Owen Anderson | 2011-10-28 | 1 | -0/+24 |
| * | Add some NEON stores to the VLD decoding hook that were accidentally omitted ... | Owen Anderson | 2011-10-27 | 1 | -0/+4 |
| * | ARM assembly parsing and encoding for VLD1 with writeback. | Jim Grosbach | 2011-10-25 | 1 | -4/+8 |
| * | ARM assembly parsing and encoding for VLD1 w/ writeback. | Jim Grosbach | 2011-10-24 | 1 | -4/+8 |
| * | ARM refactor am6offset usage for VLD1. | Jim Grosbach | 2011-10-24 | 1 | -12/+51 |
| * | Fix a NEON disassembly case that was broken in the recent refactorings. As m... | Owen Anderson | 2011-10-24 | 1 | -6/+0 |
| * | Move various generated tables into read-only memory, fixing up const correctn... | Benjamin Kramer | 2011-10-22 | 1 | -1/+1 |
| * | Assembly parsing for 4-register sequential variant of VLD2. | Jim Grosbach | 2011-10-21 | 1 | -18/+0 |
| * | Assembly parsing for 2-register sequential variant of VLD2. | Jim Grosbach | 2011-10-21 | 1 | -6/+0 |
| * | Assembly parsing for 4-register variant of VLD1. | Jim Grosbach | 2011-10-21 | 1 | -24/+0 |
| * | Assembly parsing for 3-register variant of VLD1. | Jim Grosbach | 2011-10-21 | 1 | -16/+0 |
| * | ARM VLD parsing and encoding. | Jim Grosbach | 2011-10-21 | 1 | -8/+0 |
| * | Tidy up. Trailing whitespace. | Jim Grosbach | 2011-10-20 | 1 | -2/+2 |
| * | Removed set, but unused variables. | Chad Rosier | 2011-10-17 | 1 | -10/+0 |
| * | Fix a non-firing assert. Change: | Richard Trieu | 2011-10-14 | 1 | -1/+1 |
| * | Fix undefined shift. Patch by Ahmed Charles. | Eli Friedman | 2011-10-13 | 1 | -1/+1 |
| * | SETEND is not allowed in an IT block. | Owen Anderson | 2011-10-13 | 1 | -0/+1 |
| * | ARM addrmode5 represents the 'U' bit of the encoding backwards. | Jim Grosbach | 2011-10-12 | 1 | -14/+17 |
| * | Thumb2 assembly parsing and encoding for LDC/STC. | Jim Grosbach | 2011-10-12 | 1 | -24/+50 |
| * | addrmode2 is gone from these, so no need for the reg0 operand. | Jim Grosbach | 2011-10-12 | 1 | -24/+0 |
| * | Fix the check for nested IT instructions in the disassembler. We need to per... | Owen Anderson | 2011-10-06 | 1 | -3/+6 |
| * | Adding back support for printing operands symbolically to ARM's new disassembler | Kevin Enderby | 2011-10-04 | 1 | -3/+211 |
| * | ARM fix encoding of VMOV.f32 and VMOV.f64 immediates. | Jim Grosbach | 2011-09-30 | 1 | -27/+0 |
| * | ASR #32 is not allowed on Thumb2 USAT and SSAT instructions. | Owen Anderson | 2011-09-26 | 1 | -0/+14 |
| * | Reapply r140412 (Thumb2 reg-reg loads cannot target SP or PC), with invalid t... | Owen Anderson | 2011-09-23 | 1 | -1/+1 |
| * | Revert r140412. This affects more instructions than intended. | Owen Anderson | 2011-09-23 | 1 | -1/+1 |
| * | Thumb2 register-shifted-register loads cannot target the PC or the SP. | Owen Anderson | 2011-09-23 | 1 | -1/+1 |
| * | tMOVSr is not allowed in an IT block either. | Owen Anderson | 2011-09-19 | 1 | -0/+1 |
| * | CPS instructions are UNPREDICTABLE inside IT blocks. | Owen Anderson | 2011-09-19 | 1 | -0/+4 |
| * | Thumb2 TBB and TBH instructions are only allowed at the end of IT blocks, not... | Owen Anderson | 2011-09-19 | 1 | -0/+2 |
| * | Thumb2 assembly parsing and encoding for TBB/TBH. | Jim Grosbach | 2011-09-19 | 1 | -0/+18 |
| * | Handle STRT (and friends) like LDRT (and friends) for decoding purposes. Por... | Owen Anderson | 2011-09-19 | 1 | -0/+3 |
| * | Bitfield mask instructions are unpredictable if the encoded LSB is higher tha... | Owen Anderson | 2011-09-16 | 1 | -1/+4 |
| * | Fix bitfield decoding based on Eli's feedback. | Owen Anderson | 2011-09-16 | 1 | -4/+3 |
| * | Thumb2 pre-indexed loads/stores use the restricted GPR set for Rt. | Owen Anderson | 2011-09-16 | 1 | -1/+1 |
| * | Fix disassembly of Thumb2 BFI instructions with bit range of [0, 32). | Owen Anderson | 2011-09-16 | 1 | -0/+4 |
| * | Fix disassembly of Thumb2 LDRSH with a #-0 offset. | Owen Anderson | 2011-09-16 | 1 | -1/+4 |
| * | Don't attach annotations to MCInst's. Instead, have the disassembler return,... | Owen Anderson | 2011-09-15 | 1 | -4/+8 |
| * | Nested IT blocks are UNPREDICTABLE. Mark them as such when disassembling them. | Owen Anderson | 2011-09-14 | 1 | -0/+4 |
| * | Port more encoding tests to decoding tests, and correct an improper Thumb2 pr... | Owen Anderson | 2011-09-12 | 1 | -0/+32 |
| * | LDM writeback is not allowed if Rn is in the target register list. | Owen Anderson | 2011-09-09 | 1 | -0/+19 |
| * | Fix assembly/disassembly of Thumb2 ADR instructions with immediate operands. | Owen Anderson | 2011-09-09 | 1 | -0/+18 |
