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* More dead code removal (using -Wunreachable-code)David Blaikie2012-01-201-1/+1
* ARM NEON VTBL/VTBX assembly parsing and encoding.Jim Grosbach2011-12-151-4/+1
* ARM NEON refactor VST2 w/ writeback instructions.Jim Grosbach2011-12-141-9/+18
* ARM NEON VST2 assembly parsing and encoding.Jim Grosbach2011-12-141-30/+0
* LLVMBuild: Remove trailing newline, which irked me.Daniel Dunbar2011-12-121-1/+0
* ARM assembly parsing and encoding for VLD2 with writeback.Jim Grosbach2011-12-091-9/+18
* Remove unused variableMatt Beaumont-Gay2011-11-301-2/+0
* ARM parsing for VLD1 all lanes, with writeback.Jim Grosbach2011-11-301-10/+6
* ARM assembly parsing and encoding for four-register VST1.Jim Grosbach2011-11-291-28/+8
* ARM assembly parsing and encoding for three-register VST1.Jim Grosbach2011-11-291-20/+8
* build/CMake: Finish removal of add_llvm_library_dependencies.Daniel Dunbar2011-11-291-8/+0
* Fix a misplaced paren bug.Owen Anderson2011-11-151-1/+1
* Fix an ambiguous decoding where we failed to properly decode VMOVv2f32 and VM...Owen Anderson2011-11-151-8/+62
* build: Attempt to rectify inconsistencies between CMake and LLVMBuild version...Daniel Dunbar2011-11-121-1/+1
* Re-apply 144430, this time with the associated isel and disassmbler bits.Jim Grosbach2011-11-121-4/+0
* Remove the unnecessary dependency on libARMCodeGen from libARMDisassembler.Benjamin Kramer2011-11-111-1/+1
* build: Add initial cut at LLVMBuild.txt files.Daniel Dunbar2011-11-031-0/+24
* The rules disallowing single-register reglist operands only apply to the POP ...Owen Anderson2011-11-021-5/+1
* Register list operands are not allowed to contain only a single register. Al...Owen Anderson2011-11-021-1/+5
* Fix disassembly of some VST1 instructions.Owen Anderson2011-11-011-5/+19
* ARM VST1 w/ writeback assembly parsing and encoding.Jim Grosbach2011-10-311-12/+16
* More not-crashing NEON disassembly updates for the vld refactoring.Owen Anderson2011-10-311-0/+4
* Reapply r143202, with a manual decoding hook for SWP. This change inadvertan...Owen Anderson2011-10-281-0/+24
* Add some NEON stores to the VLD decoding hook that were accidentally omitted ...Owen Anderson2011-10-271-0/+4
* ARM assembly parsing and encoding for VLD1 with writeback.Jim Grosbach2011-10-251-4/+8
* ARM assembly parsing and encoding for VLD1 w/ writeback.Jim Grosbach2011-10-241-4/+8
* ARM refactor am6offset usage for VLD1.Jim Grosbach2011-10-241-12/+51
* Fix a NEON disassembly case that was broken in the recent refactorings. As m...Owen Anderson2011-10-241-6/+0
* Move various generated tables into read-only memory, fixing up const correctn...Benjamin Kramer2011-10-221-1/+1
* Assembly parsing for 4-register sequential variant of VLD2.Jim Grosbach2011-10-211-18/+0
* Assembly parsing for 2-register sequential variant of VLD2.Jim Grosbach2011-10-211-6/+0
* Assembly parsing for 4-register variant of VLD1.Jim Grosbach2011-10-211-24/+0
* Assembly parsing for 3-register variant of VLD1.Jim Grosbach2011-10-211-16/+0
* ARM VLD parsing and encoding.Jim Grosbach2011-10-211-8/+0
* Tidy up. Trailing whitespace.Jim Grosbach2011-10-201-2/+2
* Removed set, but unused variables.Chad Rosier2011-10-171-10/+0
* Fix a non-firing assert. Change:Richard Trieu2011-10-141-1/+1
* Fix undefined shift. Patch by Ahmed Charles.Eli Friedman2011-10-131-1/+1
* SETEND is not allowed in an IT block.Owen Anderson2011-10-131-0/+1
* ARM addrmode5 represents the 'U' bit of the encoding backwards.Jim Grosbach2011-10-121-14/+17
* Thumb2 assembly parsing and encoding for LDC/STC.Jim Grosbach2011-10-121-24/+50
* addrmode2 is gone from these, so no need for the reg0 operand.Jim Grosbach2011-10-121-24/+0
* Fix the check for nested IT instructions in the disassembler. We need to per...Owen Anderson2011-10-061-3/+6
* Adding back support for printing operands symbolically to ARM's new disassemblerKevin Enderby2011-10-041-3/+211
* ARM fix encoding of VMOV.f32 and VMOV.f64 immediates.Jim Grosbach2011-09-301-27/+0
* ASR #32 is not allowed on Thumb2 USAT and SSAT instructions.Owen Anderson2011-09-261-0/+14
* Reapply r140412 (Thumb2 reg-reg loads cannot target SP or PC), with invalid t...Owen Anderson2011-09-231-1/+1
* Revert r140412. This affects more instructions than intended.Owen Anderson2011-09-231-1/+1
* Thumb2 register-shifted-register loads cannot target the PC or the SP.Owen Anderson2011-09-231-1/+1
* tMOVSr is not allowed in an IT block either.Owen Anderson2011-09-191-0/+1