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ARM
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Disassembler
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Author
Age
Files
Lines
*
More dead code removal (using -Wunreachable-code)
David Blaikie
2012-01-20
1
-1
/
+1
*
ARM NEON VTBL/VTBX assembly parsing and encoding.
Jim Grosbach
2011-12-15
1
-4
/
+1
*
ARM NEON refactor VST2 w/ writeback instructions.
Jim Grosbach
2011-12-14
1
-9
/
+18
*
ARM NEON VST2 assembly parsing and encoding.
Jim Grosbach
2011-12-14
1
-30
/
+0
*
LLVMBuild: Remove trailing newline, which irked me.
Daniel Dunbar
2011-12-12
1
-1
/
+0
*
ARM assembly parsing and encoding for VLD2 with writeback.
Jim Grosbach
2011-12-09
1
-9
/
+18
*
Remove unused variable
Matt Beaumont-Gay
2011-11-30
1
-2
/
+0
*
ARM parsing for VLD1 all lanes, with writeback.
Jim Grosbach
2011-11-30
1
-10
/
+6
*
ARM assembly parsing and encoding for four-register VST1.
Jim Grosbach
2011-11-29
1
-28
/
+8
*
ARM assembly parsing and encoding for three-register VST1.
Jim Grosbach
2011-11-29
1
-20
/
+8
*
build/CMake: Finish removal of add_llvm_library_dependencies.
Daniel Dunbar
2011-11-29
1
-8
/
+0
*
Fix a misplaced paren bug.
Owen Anderson
2011-11-15
1
-1
/
+1
*
Fix an ambiguous decoding where we failed to properly decode VMOVv2f32 and VM...
Owen Anderson
2011-11-15
1
-8
/
+62
*
build: Attempt to rectify inconsistencies between CMake and LLVMBuild version...
Daniel Dunbar
2011-11-12
1
-1
/
+1
*
Re-apply 144430, this time with the associated isel and disassmbler bits.
Jim Grosbach
2011-11-12
1
-4
/
+0
*
Remove the unnecessary dependency on libARMCodeGen from libARMDisassembler.
Benjamin Kramer
2011-11-11
1
-1
/
+1
*
build: Add initial cut at LLVMBuild.txt files.
Daniel Dunbar
2011-11-03
1
-0
/
+24
*
The rules disallowing single-register reglist operands only apply to the POP ...
Owen Anderson
2011-11-02
1
-5
/
+1
*
Register list operands are not allowed to contain only a single register. Al...
Owen Anderson
2011-11-02
1
-1
/
+5
*
Fix disassembly of some VST1 instructions.
Owen Anderson
2011-11-01
1
-5
/
+19
*
ARM VST1 w/ writeback assembly parsing and encoding.
Jim Grosbach
2011-10-31
1
-12
/
+16
*
More not-crashing NEON disassembly updates for the vld refactoring.
Owen Anderson
2011-10-31
1
-0
/
+4
*
Reapply r143202, with a manual decoding hook for SWP. This change inadvertan...
Owen Anderson
2011-10-28
1
-0
/
+24
*
Add some NEON stores to the VLD decoding hook that were accidentally omitted ...
Owen Anderson
2011-10-27
1
-0
/
+4
*
ARM assembly parsing and encoding for VLD1 with writeback.
Jim Grosbach
2011-10-25
1
-4
/
+8
*
ARM assembly parsing and encoding for VLD1 w/ writeback.
Jim Grosbach
2011-10-24
1
-4
/
+8
*
ARM refactor am6offset usage for VLD1.
Jim Grosbach
2011-10-24
1
-12
/
+51
*
Fix a NEON disassembly case that was broken in the recent refactorings. As m...
Owen Anderson
2011-10-24
1
-6
/
+0
*
Move various generated tables into read-only memory, fixing up const correctn...
Benjamin Kramer
2011-10-22
1
-1
/
+1
*
Assembly parsing for 4-register sequential variant of VLD2.
Jim Grosbach
2011-10-21
1
-18
/
+0
*
Assembly parsing for 2-register sequential variant of VLD2.
Jim Grosbach
2011-10-21
1
-6
/
+0
*
Assembly parsing for 4-register variant of VLD1.
Jim Grosbach
2011-10-21
1
-24
/
+0
*
Assembly parsing for 3-register variant of VLD1.
Jim Grosbach
2011-10-21
1
-16
/
+0
*
ARM VLD parsing and encoding.
Jim Grosbach
2011-10-21
1
-8
/
+0
*
Tidy up. Trailing whitespace.
Jim Grosbach
2011-10-20
1
-2
/
+2
*
Removed set, but unused variables.
Chad Rosier
2011-10-17
1
-10
/
+0
*
Fix a non-firing assert. Change:
Richard Trieu
2011-10-14
1
-1
/
+1
*
Fix undefined shift. Patch by Ahmed Charles.
Eli Friedman
2011-10-13
1
-1
/
+1
*
SETEND is not allowed in an IT block.
Owen Anderson
2011-10-13
1
-0
/
+1
*
ARM addrmode5 represents the 'U' bit of the encoding backwards.
Jim Grosbach
2011-10-12
1
-14
/
+17
*
Thumb2 assembly parsing and encoding for LDC/STC.
Jim Grosbach
2011-10-12
1
-24
/
+50
*
addrmode2 is gone from these, so no need for the reg0 operand.
Jim Grosbach
2011-10-12
1
-24
/
+0
*
Fix the check for nested IT instructions in the disassembler. We need to per...
Owen Anderson
2011-10-06
1
-3
/
+6
*
Adding back support for printing operands symbolically to ARM's new disassembler
Kevin Enderby
2011-10-04
1
-3
/
+211
*
ARM fix encoding of VMOV.f32 and VMOV.f64 immediates.
Jim Grosbach
2011-09-30
1
-27
/
+0
*
ASR #32 is not allowed on Thumb2 USAT and SSAT instructions.
Owen Anderson
2011-09-26
1
-0
/
+14
*
Reapply r140412 (Thumb2 reg-reg loads cannot target SP or PC), with invalid t...
Owen Anderson
2011-09-23
1
-1
/
+1
*
Revert r140412. This affects more instructions than intended.
Owen Anderson
2011-09-23
1
-1
/
+1
*
Thumb2 register-shifted-register loads cannot target the PC or the SP.
Owen Anderson
2011-09-23
1
-1
/
+1
*
tMOVSr is not allowed in an IT block either.
Owen Anderson
2011-09-19
1
-0
/
+1
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