| Commit message (Expand) | Author | Age | Files | Lines |
|---|
| * | Fix #13035, a bug around Thumb instruction LDRD/STRD with negative #0 offset ... | Jiangning Liu | 2012-08-02 | 1 | -12/+19 |
| * | Fix #13241, a bug around shift immediate operand for ARM instruction ADR. | Jiangning Liu | 2012-08-02 | 2 | -0/+20 |
| * | ARM: Define generic HINT instruction. | Jim Grosbach | 2012-06-18 | 1 | -0/+21 |
| * | Fix the encoding of the armv7m (MClass) for MSR registers other than aspr, | Kevin Enderby | 2012-06-15 | 1 | -10/+20 |
| * | Fix the encoding of the armv7m (MClass) for MSR APSR writes which was missing | Kevin Enderby | 2012-05-17 | 1 | -5/+23 |
| * | Fixed the LLVM ARM v7 assembler and instruction printer for 8-bit immediate o... | Silviu Baranga | 2012-05-11 | 1 | -2/+6 |
| * | Refactor IT handling not to store the bottom bit of the condition code in the... | Richard Barton | 2012-04-27 | 1 | -1/+2 |
| * | For ARM disassembly only print 32 unsigned bits for the address of branch | Kevin Enderby | 2012-04-13 | 1 | -2/+2 |
| * | Move getOpcodeName from the various target InstPrinters into the superclass M... | Benjamin Kramer | 2012-04-02 | 2 | -5/+0 |
| * | Remove getInstructionName from MCInstPrinter implementations in favor of usin... | Craig Topper | 2012-04-02 | 2 | -4/+2 |
| * | Make MCInstrInfo available to the MCInstPrinter. This will be used to remove ... | Craig Topper | 2012-04-02 | 2 | -3/+4 |
| * | ARM more NEON VLD/VST composite physical register refactoring. | Jim Grosbach | 2012-03-06 | 1 | -5/+4 |
| * | ARM refactor more NEON VLD/VST instructions to use composite physregs | Jim Grosbach | 2012-03-06 | 2 | -23/+11 |
| * | Tidy up. Kill some dead code. | Jim Grosbach | 2012-03-06 | 2 | -10/+0 |
| * | ARM Refactor VLD/VST spaced pair instructions. | Jim Grosbach | 2012-03-05 | 2 | -0/+11 |
| * | ARM refactor away a bunch of VLD/VST pseudo instructions. | Jim Grosbach | 2012-03-05 | 2 | -0/+10 |
| * | Make MCRegisterInfo available to the the MCInstPrinter. | Jim Grosbach | 2012-03-05 | 2 | -2/+4 |
| * | Change ARMInstPrinter::printPredicateOperand() so it will not abort if it | Kevin Enderby | 2012-03-01 | 1 | -1/+4 |
| * | Remove dead code. Improve llvm_unreachable text. Simplify some control flow. | Ahmed Charles | 2012-02-19 | 1 | -1/+0 |
| * | Emacs-tag and some comment fix for all ARM, CellSPU, Hexagon, MBlaze, MSP430,... | Jia Liu | 2012-02-18 | 1 | -1/+1 |
| * | Convert assert(0) to llvm_unreachable | Craig Topper | 2012-02-07 | 1 | -2/+2 |
| * | NEON VLD4(all lanes) assembly parsing and encoding. | Jim Grosbach | 2012-01-25 | 2 | -1/+29 |
| * | NEON VLD3(all lanes) assembly parsing and encoding. | Jim Grosbach | 2012-01-24 | 2 | -0/+26 |
| * | NEON VLD4(multiple 4 element structures) assembly parsing. | Jim Grosbach | 2012-01-24 | 2 | -0/+14 |
| * | NEON VLD3(multiple 3-element structures) assembly parsing. | Jim Grosbach | 2012-01-23 | 2 | -0/+12 |
| * | ARM VFP assembly parsing and encoding for VCVT(float <--> fixed point). | Jim Grosbach | 2011-12-22 | 2 | -0/+12 |
| * | ARM NEON VLD2 assembly parsing for structure to all lanes, non-writeback. | Jim Grosbach | 2011-12-21 | 2 | -0/+12 |
| * | ARM assembly parsing and encoding support for LDRD(label). | Jim Grosbach | 2011-12-19 | 1 | -0/+11 |
| * | ARM NEON VST2 assembly parsing and encoding. | Jim Grosbach | 2011-12-14 | 2 | -0/+12 |
| * | LLVMBuild: Remove trailing newline, which irked me. | Daniel Dunbar | 2011-12-12 | 1 | -1/+0 |
| * | ARM parsing for VLD1 two register all lanes, no writeback. | Jim Grosbach | 2011-11-30 | 2 | -0/+11 |
| * | ARM parsing aliases for VLD1 single register all lanes. | Jim Grosbach | 2011-11-30 | 2 | -0/+9 |
| * | build/CMake: Finish removal of add_llvm_library_dependencies. | Daniel Dunbar | 2011-11-29 | 1 | -5/+0 |
| * | Simplify some uses of utohexstr. | Benjamin Kramer | 2011-11-07 | 1 | -2/+2 |
| * | build: Add initial cut at LLVMBuild.txt files. | Daniel Dunbar | 2011-11-03 | 1 | -0/+24 |
| * | Fix the issue that r143552 was trying to address the _right_ way. One-regist... | Owen Anderson | 2011-11-02 | 1 | -2/+6 |
| * | Assembly parsing for 4-register variant of VLD1. | Jim Grosbach | 2011-10-21 | 2 | -0/+12 |
| * | Assembly parsing for 3-register variant of VLD1. | Jim Grosbach | 2011-10-21 | 2 | -0/+11 |
| * | ARM VLD parsing and encoding. | Jim Grosbach | 2011-10-21 | 2 | -0/+10 |
| * | whitespace. | Jim Grosbach | 2011-10-21 | 1 | -1/+1 |
| * | ARM VTBL (one register) assembly parsing and encoding. | Jim Grosbach | 2011-10-18 | 2 | -0/+6 |
| * | ARM parsing and encoding for the <option> form of LDC/STC instructions. | Jim Grosbach | 2011-10-12 | 2 | -0/+6 |
| * | 80 columns. | Jim Grosbach | 2011-10-12 | 1 | -2/+1 |
| * | Tidy up. Formatting. | Jim Grosbach | 2011-10-12 | 1 | -2/+2 |
| * | ARM NEON assembly parsing and encoding for VDUP(scalar). | Jim Grosbach | 2011-10-07 | 2 | -0/+6 |
| * | Support a valid, but not very useful, encoding of CPSIE where none of the AIF... | Owen Anderson | 2011-10-05 | 1 | -0/+3 |
| * | Adding back support for printing operands symbolically to ARM's new disassembler | Kevin Enderby | 2011-10-04 | 1 | -1/+12 |
| * | ARM fix encoding of VMOV.f32 and VMOV.f64 immediates. | Jim Grosbach | 2011-09-30 | 2 | -34/+4 |
| * | Check in a patch that has already been code reviewed by Owen that I'd forgott... | James Molloy | 2011-09-28 | 1 | -0/+20 |
| * | Post-index loads/stores in still need to print the post-indexed immediate, ev... | Owen Anderson | 2011-09-23 | 1 | -3/+3 |
