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path: root/lib/Target/ARM/Thumb1RegisterInfo.cpp
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* Remove predicates when changing an add into an unpredicable mov.Jakob Stoklund Olesen2010-01-191-2/+6
* improve portability to avoid conflicting with std::next in c++'0x.Chris Lattner2009-12-031-1/+1
* Use Unified Assembly Syntax for the ARM backend.Jim Grosbach2009-11-091-1/+1
* 80-column cleanup of file header commentsJim Grosbach2009-11-071-2/+3
* Cleanup now that frame index scavenging via post-pass is working for ARM and ...Jim Grosbach2009-10-281-12/+0
* Trim more includes.Evan Cheng2009-10-221-1/+0
* Missing piece of the ARM frame index post-scavenging conditionalizationJim Grosbach2009-10-211-0/+12
* Now that all ARM subtargets use frame index scavenging, the Thumb1 requires*Jim Grosbach2009-10-201-12/+0
* Enable allocation of R3 in Thumb1Jim Grosbach2009-10-191-1/+0
* Adjust the scavenge register spilling to allow the target to choose anJim Grosbach2009-10-191-15/+32
* Cleanup up unused R3LiveIn tracking.Jim Grosbach2009-10-081-9/+0
* Re-enable register scavenging in Thumb1 by default.Jim Grosbach2009-10-081-64/+9
* reverting thumb1 scavenging default due to test failure while I figure out wh...Jim Grosbach2009-10-071-8/+64
* Enable thumb1 register scavenging by default.Jim Grosbach2009-10-071-64/+8
* Add register-reuse to frame-index register scavenging. When a target usesJim Grosbach2009-10-071-13/+19
* In Thumb1, the register scavenger is not always able to use an emergencyJim Grosbach2009-10-051-0/+25
* ARM::tPOP and tPOP_RET each has an extra writeback operand now.Evan Cheng2009-10-011-0/+1
* Start of revamping the register scavenging in PEI. ARM Thumb1 is the drivingJim Grosbach2009-09-241-53/+83
* Remove some unused variables and methods warned about byDuncan Sands2009-09-061-2/+1
* Push LLVMContexts through the IntegerType APIs.Owen Anderson2009-08-131-1/+2
* Shrinkify Thumb2 load / store multiple instructions.Evan Cheng2009-08-111-1/+1
* Whitespace cleanup. Remove trailing whitespace.Jim Grosbach2009-08-111-1/+1
* Rename MVT to EVT, in preparation for splitting SimpleValueType out into its ...Owen Anderson2009-08-101-1/+1
* tADDrSPI doesn't have a predicate operand, but tADDhirr and tADDi3 have.Evan Cheng2009-07-281-0/+5
* - More refactoring. This gets rid of all of the getOpcode calls.Evan Cheng2009-07-281-2/+2
* Rename tMOVhi2lor to tMOVgpr2tgpr. It's not moving from a high register to a ...Evan Cheng2009-07-261-8/+8
* Refactor. Get rid of a few more getOpcode() calls.Evan Cheng2009-07-261-0/+1
* Revert the ConstantInt constructors back to their 2.5 forms where possible, t...Owen Anderson2009-07-241-2/+1
* Correctly handle the Thumb-2 imm8 addrmode. Specialize frame index eliminatio...David Goodwin2009-07-241-0/+9
* Get rid of the Pass+Context magic.Owen Anderson2009-07-221-1/+1
* Fix PR4567. Thumb1 target was using the wrong instruction to handle sp = sub ...Evan Cheng2009-07-201-3/+11
* Fix a regression from 76124. Thumb1 instructions default to S bit being true.Evan Cheng2009-07-191-13/+14
* Emit cross regclass register moves for thumb2.Anton Korobeynikov2009-07-161-10/+0
* Let callers decide the sub-register index on the def operand of rematerialize...Evan Cheng2009-07-161-6/+8
* Move EVER MORE stuff over to LLVMContext.Owen Anderson2009-07-141-1/+4
* llvm_unreachable->llvm_unreachable(0), LLVM_UNREACHABLE->llvm_unreachable.Torok Edwin2009-07-141-1/+1
* Major changes to Thumb (not Thumb2). Many 16-bit instructions either modifies...Evan Cheng2009-07-111-28/+96
* Implement changes from Chris's feedback.Torok Edwin2009-07-081-0/+1
* Generalize opcode selection in ARMBaseRegisterInfo.David Goodwin2009-07-081-5/+6
* Push methods into base class in preparation for sharing.David Goodwin2009-07-081-6/+7
* Start converting to new error handling API.Torok Edwin2009-07-081-2/+2
* Checkpoint refactoring of ThumbInstrInfo and ThumbRegisterInfo into Thumb1Ins...David Goodwin2009-07-021-0/+755
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