| Commit message (Expand) | Author | Age | Files | Lines |
|---|
| * | Don't cache the instruction and register info from the TargetMachine, because | Bill Wendling | 2013-06-07 | 1 | -3/+9 |
| * | Allow the register scavenger to spill multiple registers | Hal Finkel | 2013-03-22 | 1 | -1/+1 |
| * | Move the eliminateCallFramePseudoInstr method from TargetRegisterInfo | Eli Bendersky | 2013-02-21 | 1 | -41/+0 |
| * | [PEI] Pass the frame index operand number to the eliminateFrameIndex function. | Chad Rosier | 2013-01-31 | 1 | -15/+12 |
| * | Move all of the header files which are involved in modelling the LLVM IR | Chandler Carruth | 2013-01-02 | 1 | -4/+4 |
| * | Remove the explicit MachineInstrBuilder(MI) constructor. | Jakob Stoklund Olesen | 2012-12-19 | 1 | -6/+3 |
| * | Use the new script to sort the includes of every file under lib. | Chandler Carruth | 2012-12-03 | 1 | -6/+6 |
| * | Add an MF argument to TRI::getPointerRegClass() and TII::getRegClass(). | Jakob Stoklund Olesen | 2012-05-07 | 1 | -1/+2 |
| * | Convert more uses of XXXRegisterClass to &XXXRegClass. No functional change s... | Craig Topper | 2012-04-20 | 1 | -4/+4 |
| * | Reorder includes to match coding standards. Fix an issue or two exposed by that. | Craig Topper | 2012-03-17 | 1 | -2/+1 |
| * | Handle regmasks in Thumb1RegisterInfo::saveScavengerRegister(). | Jakob Stoklund Olesen | 2012-03-01 | 1 | -0/+5 |
| * | Enable ARM base pointer when calling functions with large arguments. | Jakob Stoklund Olesen | 2012-02-28 | 1 | -0/+16 |
| * | Emacs-tag and some comment fix for all ARM, CellSPU, Hexagon, MBlaze, MSP430,... | Jia Liu | 2012-02-18 | 1 | -1/+1 |
| * | Convert assert(0) to llvm_unreachable | Craig Topper | 2012-02-07 | 1 | -1/+1 |
| * | Add bundle aware API for querying instruction properties and switch the code | Evan Cheng | 2011-12-07 | 1 | -4/+3 |
| * | Fix a regression from r138445. If we're loading from the frame/base pointer | Chad Rosier | 2011-10-10 | 1 | -0/+1 |
| * | Thumb1 ADD/SUB SP instructions are predicable in Thumb2 mode. | Jim Grosbach | 2011-08-24 | 1 | -14/+6 |
| * | 80 columns. | Jim Grosbach | 2011-08-17 | 1 | -1/+2 |
| * | Tidy up. | Jim Grosbach | 2011-08-17 | 1 | -2/+1 |
| * | Silence a bunch (but not all) "variable written but not read" warnings | Duncan Sands | 2011-08-12 | 1 | -2/+2 |
| * | Sink ARMMCExpr and ARMAddressingModes into MC layer. First step to separate A... | Evan Cheng | 2011-07-20 | 1 | -1/+1 |
| * | Move getInitialFrameState from TargetFrameInfo to MCAsmInfo (suggestions for | Evan Cheng | 2011-07-18 | 1 | -1/+0 |
| * | Refact ARM Thumb1 tMOVr instruction family. | Jim Grosbach | 2011-06-30 | 1 | -3/+3 |
| * | Thumb1 register to register MOV instruction is predicable. | Jim Grosbach | 2011-06-30 | 1 | -11/+11 |
| * | Refactor away tSpill and tRestore pseudos in ARM backend. | Jim Grosbach | 2011-06-29 | 1 | -5/+3 |
| * | - Rename TargetInstrDesc, TargetOperandInfo to MCInstrDesc and MCOperandInfo and | Evan Cheng | 2011-06-28 | 1 | -8/+8 |
| * | Use TRI::has{Sub,Super}ClassEq() where possible. | Jakob Stoklund Olesen | 2011-06-02 | 1 | -1/+1 |
| * | Add a TRI::getLargestLegalSuperClass hook to provide an upper limit on regist... | Jakob Stoklund Olesen | 2011-04-26 | 1 | -0/+8 |
| * | Trim a few unneeded includes. | Jim Grosbach | 2011-04-18 | 1 | -2/+0 |
| * | Provide a legal pointer register class when targeting thumb1. | Jakob Stoklund Olesen | 2011-03-31 | 1 | -0/+5 |
| * | In Thumb1 mode the constant might be materialized via the load from constpool... | Anton Korobeynikov | 2011-03-05 | 1 | -3/+3 |
| * | Implement frame unwinding information emission for Thumb1. Not finished yet b... | Anton Korobeynikov | 2011-03-05 | 1 | -25/+35 |
| * | Preliminary support for ARM frame save directives emission via MI flags. | Anton Korobeynikov | 2011-03-05 | 1 | -13/+13 |
| * | When updating a tSpill/tRestore instruction to be a tSTRr/tLDRr, correctly | Jim Grosbach | 2011-01-13 | 1 | -4/+7 |
| * | Rename TargetFrameInfo into TargetFrameLowering. Also, put couple of FIXMEs a... | Anton Korobeynikov | 2011-01-10 | 1 | -4/+4 |
| * | If we're not using reg+reg offset we're using reg+imm, set the opcode | Eric Christopher | 2010-12-21 | 1 | -2/+2 |
| * | Add tSpill and tRestore to the opcodes to replace with tSTRi and tLDRi | Bill Wendling | 2010-12-16 | 1 | -0/+2 |
| * | Thumb1 had two patterns for the same load-from-constant-pool instruction. | Jim Grosbach | 2010-12-15 | 1 | -1/+1 |
| * | If we're changing the frame register to a physical register other than SP, we | Bill Wendling | 2010-12-15 | 1 | -27/+37 |
| * | The tLDR et al instructions were emitting either a reg/reg or reg/imm | Bill Wendling | 2010-12-14 | 1 | -7/+4 |
| * | Avoid release build warnings. | Benjamin Kramer | 2010-11-19 | 1 | -2/+2 |
| * | Move hasFP() and few related hooks to TargetFrameInfo. | Anton Korobeynikov | 2010-11-18 | 1 | -15/+5 |
| * | First step of huge frame-related refactoring: move emit{Prologue,Epilogue} ou... | Anton Korobeynikov | 2010-11-15 | 1 | -203/+0 |
| * | Revert r114340 (improvements in Darwin function prologue/epilogue), as it broke | Jim Grosbach | 2010-11-02 | 1 | -11/+27 |
| * | Add a pre-dispatch SjLj EH hook on the unwind edge for targets to do any | Jim Grosbach | 2010-10-19 | 1 | -8/+7 |
| * | Simplify ARM callee-saved register handling by removing the distinction | Jim Grosbach | 2010-09-20 | 1 | -27/+11 |
| * | Re-apply r112883: | Jim Grosbach | 2010-09-03 | 1 | -3/+13 |
| * | Revert "For ARM stack frames that utilize variable sized objects and have eit... | Daniel Dunbar | 2010-09-03 | 1 | -13/+3 |
| * | For ARM stack frames that utilize variable sized objects and have either | Jim Grosbach | 2010-09-02 | 1 | -3/+13 |
| * | Simplify eliminateFrameIndex() interface back down now that PEI doesn't need | Jim Grosbach | 2010-08-26 | 1 | -13/+4 |
