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* ARM: Remove unused variable.Benjamin Kramer2013-04-081-2/+0
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179001 91177308-0d34-0410-b5e6-96231b3b80d8
* Avoid high-latency false CPSR dependencies even for tMOVSi.Jakob Stoklund Olesen2013-04-041-46/+103
| | | | | | | | | | | | | | | | | The Thumb2SizeReduction pass avoids false CPSR dependencies, except it still aggressively creates tMOVi8 instructions because they are so common. Avoid creating false CPSR dependencies even for tMOVi8 instructions when the the CPSR flags are known to have high latency. This allows integer computation to overlap floating point computations. Also process blocks in a reverse post-order and propagate high-latency flags to successors. <rdar://problem/13468102> git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178773 91177308-0d34-0410-b5e6-96231b3b80d8
* Move all of the header files which are involved in modelling the LLVM IRChandler Carruth2013-01-021-1/+1
| | | | | | | | | | | | | | | | | | | | | into their new header subdirectory: include/llvm/IR. This matches the directory structure of lib, and begins to correct a long standing point of file layout clutter in LLVM. There are still more header files to move here, but I wanted to handle them in separate commits to make tracking what files make sense at each layer easier. The only really questionable files here are the target intrinsic tablegen files. But that's a battle I'd rather not fight today. I've updated both CMake and Makefile build systems (I think, and my tests think, but I may have missed something). I've also re-sorted the includes throughout the project. I'll be committing updates to Clang, DragonEgg, and Polly momentarily. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@171366 91177308-0d34-0410-b5e6-96231b3b80d8
* Resort the #include lines in include/... and lib/... with theChandler Carruth2013-01-021-1/+1
| | | | | | | | | | utils/sort_includes.py script. Most of these are updating the new R600 target and fixing up a few regressions that have creeped in since the last time I sorted the includes. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@171362 91177308-0d34-0410-b5e6-96231b3b80d8
* Remove the Function::getFnAttributes method in favor of using the AttributeSetBill Wendling2012-12-301-3/+5
| | | | | | | | | | directly. This is in preparation for removing the use of the 'Attribute' class as a collection of attributes. That will shift to the AttributeSet class instead. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@171253 91177308-0d34-0410-b5e6-96231b3b80d8
* On some ARM cpus, flags setting movs with shifter operand, i.e. lsl, lsr, asr,Evan Cheng2012-12-201-77/+92
| | | | | | | | | | are more expensive than the non-flag setting variant. Teach thumb2 size reduction pass to avoid generating them unless we are optimizing for size. rdar://12892707 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@170728 91177308-0d34-0410-b5e6-96231b3b80d8
* Rename the 'Attributes' class to 'Attribute'. It's going to represent a ↵Bill Wendling2012-12-191-1/+1
| | | | | | single attribute in the future. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@170502 91177308-0d34-0410-b5e6-96231b3b80d8
* Disable ARM partial flag dependency optimization at -OzQuentin Colombet2012-12-181-2/+10
| | | | | | | | | To not over constrain the scheduler for ARM in thumb mode, some optimizations for code size reduction, specific to ARM thumb, are blocked when they add a dependency (like write after read dependency). Disables this check when code size is the priority, i.e., code is compiled with -Oz. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@170462 91177308-0d34-0410-b5e6-96231b3b80d8
* Repair bundles that were broken by removing and reinserting the firstJakob Stoklund Olesen2012-12-181-1/+8
| | | | | | | | | | instruction. This isn't strictly necessary at the moment because Thumb2SizeReduction also copies all MI flags from the old instruction to the new. However, a future patch will make that kind of direct flag tampering illegal. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@170395 91177308-0d34-0410-b5e6-96231b3b80d8
* Extract a method, no functional change intended.Jakob Stoklund Olesen2012-12-181-31/+35
| | | | | | Sadly, this costs us a perfectly good opportunity to use 'goto'. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@170385 91177308-0d34-0410-b5e6-96231b3b80d8
* Use the new script to sort the includes of every file under lib.Chandler Carruth2012-12-031-5/+5
| | | | | | | | | | | | | | | | | Sooooo many of these had incorrect or strange main module includes. I have manually inspected all of these, and fixed the main module include to be the nearest plausible thing I could find. If you own or care about any of these source files, I encourage you to take some time and check that these edits were sensible. I can't have broken anything (I strictly added headers, and reordered them, never removed), but they may not be the headers you'd really like to identify as containing the API being implemented. Many forward declarations and missing includes were added to a header files to allow them to parse cleanly when included first. The main module rule does in fact have its merits. =] git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@169131 91177308-0d34-0410-b5e6-96231b3b80d8
* Revert r162713: "Add ATOMIC_LDR* pseudo-instructions to model atomic_load on ↵Jakob Stoklund Olesen2012-08-281-21/+5
| | | | | | | | | | | ARM." This wasn't the right way to enforce ordering of atomics. We are already setting the isVolatile bit on memory operands of atomic operations which is good enough to enforce the correct ordering. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162732 91177308-0d34-0410-b5e6-96231b3b80d8
* Add ATOMIC_LDR* pseudo-instructions to model atomic_load on ARM.Jakob Stoklund Olesen2012-08-271-5/+21
| | | | | | | | | | | It is not safe to use normal LDR instructions because they may be reordered by the scheduler. The ATOMIC_LDR pseudos have a mayStore flag that prevents reordering. Atomic loads are also prevented from participating in rematerialization and load folding. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162713 91177308-0d34-0410-b5e6-96231b3b80d8
* Added missing CMN case in Thumb2SizeReduction pass so that LLVM emits ↵Sebastian Pop2012-05-041-0/+1
| | | | | | 16-bits encoding of CMN instructions. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156195 91177308-0d34-0410-b5e6-96231b3b80d8
* Tidy up. 80 columns.Jim Grosbach2012-04-061-1/+1
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@154226 91177308-0d34-0410-b5e6-96231b3b80d8
* Use uint16_t to store registers and opcode in static tables in the target ↵Craig Topper2012-03-111-3/+3
| | | | | | specific backends. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152537 91177308-0d34-0410-b5e6-96231b3b80d8
* Use uint16_t to store instruction implicit uses and defs. Reduces static data.Craig Topper2012-03-081-1/+1
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152301 91177308-0d34-0410-b5e6-96231b3b80d8
* Make sure the regs are low regs for tMUL size reduction.Jim Grosbach2012-02-241-1/+6
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@151318 91177308-0d34-0410-b5e6-96231b3b80d8
* Thumb2 size reduction fix for tied operands of tMUL.Jim Grosbach2012-02-241-1/+13
| | | | | | | | | The tied source operand of tMUL is the second source operand, not the first like every other two-address thumb instruction. Special case it in the size reduction pass to make sure we create the tMUL instruction properly. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@151315 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix a CPSR liveness tracking bug introduced when I converted IT block to bundle.Evan Cheng2011-12-171-4/+7
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146805 91177308-0d34-0410-b5e6-96231b3b80d8
* - Add MachineInstrBundle.h and MachineInstrBundle.cpp. This includes a functionEvan Cheng2011-12-141-13/+28
| | | | | | | | | | | to finalize MI bundles (i.e. add BUNDLE instruction and computing register def and use lists of the BUNDLE instruction) and a pass to unpack bundles. - Teach more of MachineBasic and MachineInstr methods to be bundle aware. - Switch Thumb2 IT block to MI bundles and delete the hazard recognizer hack to prevent IT blocks from being broken apart. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146542 91177308-0d34-0410-b5e6-96231b3b80d8
* Add bundle aware API for querying instruction properties and switch the codeEvan Cheng2011-12-071-3/+2
| | | | | | | | | | | | | | | generator to it. For non-bundle instructions, these behave exactly the same as the MC layer API. For properties like mayLoad / mayStore, look into the bundle and if any of the bundled instructions has the property it would return true. For properties like isPredicable, only return true if *all* of the bundled instructions have the property. For properties like canFoldAsLoad, isCompare, conservatively return false for bundles. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146026 91177308-0d34-0410-b5e6-96231b3b80d8
* Avoid partial CPSR dependency from loop backedges. rdar://10357570Evan Cheng2011-10-271-24/+43
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@143145 91177308-0d34-0410-b5e6-96231b3b80d8
* Thumb1 ADD/SUB SP instructions are predicable in Thumb2 mode.Jim Grosbach2011-08-241-0/+1
| | | | | | | | | | Add the predicate operand to the instructions. Update the back end accordingly where the instructions are used. Restrict the SP operands to actually only be SP, as otherwise these break assembly parsing for the normal instruction variants. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138445 91177308-0d34-0410-b5e6-96231b3b80d8
* ARM extend instructions simplification.Jim Grosbach2011-07-271-5/+13
| | | | | | | | | Refactor the SXTB, SXTH, SXTB16, UXTB, UXTH, and UXTB16 instructions to not have an 'r' and an 'r_rot' version, but just a single version with a rotate that can be zero. Use plain Pat<>'s for the ISel of the non-rotated version. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136225 91177308-0d34-0410-b5e6-96231b3b80d8
* Sink ARMMCExpr and ARMAddressingModes into MC layer. First step to separate ↵Evan Cheng2011-07-201-1/+1
| | | | | | ARM MC code from target. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135636 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix off-by-one error.Jim Grosbach2011-07-011-1/+1
| | | | | | (low two bits always zero, so off by one bit of encoded value). git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134247 91177308-0d34-0410-b5e6-96231b3b80d8
* Pseudo-ize t2MOVCC[ri].Jim Grosbach2011-07-011-2/+0
| | | | | | | | | | t2MOVCC[ri] are just t2MOV[ri] instructions, so properly pseudo-ize them. The Thumb1 versions, tMOVCC[ri] were only present for use by the size- reduction pass, so they're no longer necessary at all and can be deleted. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134242 91177308-0d34-0410-b5e6-96231b3b80d8
* Refact ARM Thumb1 tMOVr instruction family.Jim Grosbach2011-06-301-1/+1
| | | | | | | | | | | Merge the tMOVr, tMOVgpr2tgpr, tMOVtgpr2gpr, and tMOVgpr2gpr instructions into tMOVr. There's no need to keep them separate. Giving the tMOVr instruction the proper GPR register class for its operands is sufficient to give the register allocator enough information to do the right thing directly. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134204 91177308-0d34-0410-b5e6-96231b3b80d8
* Size reducing SP adjusting t2ADDri needs to check predication.Jim Grosbach2011-06-301-1/+4
| | | | | | | | | tADDrSPi is not predicable, so we can't size-reduce a t2ADDri to it if the predicate is anything other than "always." git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134130 91177308-0d34-0410-b5e6-96231b3b80d8
* Remove redundant Thumb2 ADD/SUB SP instruction definitions.Jim Grosbach2011-06-291-26/+47
| | | | | | | | | | | | Unlike Thumb1, Thumb2 does not have dedicated encodings for adjusting the stack pointer. It can just use the normal add-register-immediate encoding since it can use all registers as a source, not just R0-R7. The extra instruction definitions are just duplicates of the normal instructions with the (not well enforced) constraint that the source register was SP. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134114 91177308-0d34-0410-b5e6-96231b3b80d8
* - Rename TargetInstrDesc, TargetOperandInfo to MCInstrDesc and MCOperandInfo andEvan Cheng2011-06-281-34/+34
| | | | | | | | | sink them into MC layer. - Added MCInstrInfo, which captures the tablegen generated static data. Chang TargetInstrInfo so it's based off MCInstrInfo. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134021 91177308-0d34-0410-b5e6-96231b3b80d8
* use the MachineInstrBuilder operator-> to simplify some code.Chris Lattner2011-04-291-1/+1
| | | | | | | There are probably more instances of this floating around. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@130474 91177308-0d34-0410-b5e6-96231b3b80d8
* Avoid some 's' 16-bit instruction which partially update CPSRBob Wilson2011-04-191-85/+165
| | | | | | | (and add false dependency) when it isn't dependent on last CPSR defining instruction. rdar://8928208 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129773 91177308-0d34-0410-b5e6-96231b3b80d8
* Handle MI flags inside Thumb2SizeReduction pass.Anton Korobeynikov2011-03-051-0/+9
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127102 91177308-0d34-0410-b5e6-96231b3b80d8
* Revert both r121082 (which broke a bunch of constant pool stuff) and r125074 ↵Owen Anderson2011-02-081-43/+9
| | | | | | (which worked around it). This should get us back to the old, correct behavior, though it will make the integrated assembler unhappy for the time being. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@125127 91177308-0d34-0410-b5e6-96231b3b80d8
* Temporary workaround for a bad bug introduced by r121082 which replacedEvan Cheng2011-02-081-8/+5
| | | | | | | | | | | | | t2LDRpci with t2LDRi12. There are a couple of problems with this. 1. The encoding for the literal and immediate constant are different. Note bit 7 of the literal case is 'U' so it can be negative. 2. t2LDRi12 is now narrowed to tLDRpci before constant island pass is run. So we end up never using the Thumb2 instruction, which ends up creating a lot more constant islands. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@125074 91177308-0d34-0410-b5e6-96231b3b80d8
* The tLDR et al instructions were emitting either a reg/reg or reg/immBill Wendling2010-12-141-29/+36
| | | | | | | | | | | | | | | | | instruction based on the t_addrmode_s# mode and what it returned. There is some obvious badness to this. In particular, it's hard to do MC-encoding when the instruction may change out from underneath you after the t_addrmode_s# variable is finally resolved. The solution is to revert a long-ago change that merged the reg/reg and reg/imm versions. There is the addition of several new addressing modes. They no longer have extraneous operands associated with them. I.e., if it's reg/reg we don't have to have a dummy zero immediate tacked on to the SDNode. There are some obvious cleanups here, which will happen shortly. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121747 91177308-0d34-0410-b5e6-96231b3b80d8
* Refactor the ARM CMPz* patterns to just use the normal CMP instructions whenJim Grosbach2010-12-071-5/+3
| | | | | | | possible. They were duplicates for everything exception the source pattern before. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121179 91177308-0d34-0410-b5e6-96231b3b80d8
* Second attempt at converting Thumb2's LDRpci, including updating the ↵Owen Anderson2010-12-071-6/+42
| | | | | | gazillion places that need to know about it. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121082 91177308-0d34-0410-b5e6-96231b3b80d8
* The Thumb tADDrSPi instruction is not valid when the destination is SP.Bob Wilson2010-12-041-1/+8
| | | | | | Check for that and try narrowing it to tADDspi instead. Radar 8724703. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@120892 91177308-0d34-0410-b5e6-96231b3b80d8
* Correctly size-reduce the t2CMPzrr instruction to tCMPzr when possible.Jim Grosbach2010-12-031-1/+13
| | | | | | | tCMPzhir has undefined behavior when both source registers are low registers. rdar://8728577 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@120858 91177308-0d34-0410-b5e6-96231b3b80d8
* Reduce t2 ldr/str instructions to the correct t1 versions when there's anJim Grosbach2010-12-031-6/+6
| | | | | | immediate offset. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@120833 91177308-0d34-0410-b5e6-96231b3b80d8
* Size reduction for tPUSH come from t2STMDB_UPD, not t2STMIA_UPD.Jim Grosbach2010-12-031-1/+2
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@120822 91177308-0d34-0410-b5e6-96231b3b80d8
* Encode the multi-load/store instructions with their respective modes ('ia',Bill Wendling2010-11-161-19/+24
| | | | | | | | | | 'db', 'ib', 'da') instead of having that mode as a separate field in the instruction. It's more convenient for the asm parser and much more readable for humans. <rdar://problem/8654088> git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119310 91177308-0d34-0410-b5e6-96231b3b80d8
* Clarify commentJim Grosbach2010-09-141-2/+2
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@113846 91177308-0d34-0410-b5e6-96231b3b80d8
* To shrink a t2LDM instruction to the 16-bit wide tLDM instruction, the baseJim Grosbach2010-09-071-0/+12
| | | | | | | | | | | | register must be one of the destination registers for the load. Otherwise, the tLDM instruction will write-back to the base register, which isn't what's desired (otherwise, we'd have a t2LDM_UPD instead). rdar://8394087 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@113297 91177308-0d34-0410-b5e6-96231b3b80d8
* Reapply r110396, with fixes to appease the Linux buildbot gods.Owen Anderson2010-08-061-1/+1
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110460 91177308-0d34-0410-b5e6-96231b3b80d8
* Revert r110396 to fix buildbots.Owen Anderson2010-08-061-1/+1
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110410 91177308-0d34-0410-b5e6-96231b3b80d8
* Don't use PassInfo* as a type identifier for passes. Instead, use the ↵Owen Anderson2010-08-051-1/+1
| | | | | | | | | address of the static ID member as the sole unique type identifier. Clean up APIs related to this change. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110396 91177308-0d34-0410-b5e6-96231b3b80d8
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