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* ARMAsmBackend.cpp: Use Triple::isOSBinFormatCOFF() instead of isOSWindows().NAKAMURA Takumi2013-06-111-1/+1
* Whitespace.NAKAMURA Takumi2013-06-111-5/+5
* ARM: diagnose ARM/Thumb assembly switches on CPUs only supporting one.Tim Northover2013-06-103-1/+23
* Silencing an MSVC warning about comparing signed and unsigned values.Aaron Ballman2013-06-101-1/+1
* Fix misleading comments in ARMAsmParserAmaury de la Vieuville2013-06-101-6/+6
* ARM: ISB cannot be passed the same options as DMBAmaury de la Vieuville2013-06-107-2/+157
* Fix ARM unwind opcode assembler in several cases.Logan Chien2013-06-093-169/+185
* ARM FastISel fix load register classesJF Bastien2013-06-091-4/+4
* ARM: fix VMOVvnf32 decoding when ambiguous with VCVTAmaury de la Vieuville2013-06-081-0/+4
* ARM: enforce SRS decoding constraintsAmaury de la Vieuville2013-06-081-1/+7
* ARM: fix CPS decoding when ambiguous with QADDAmaury de la Vieuville2013-06-082-0/+34
* ARM: fix VCVT decodingAmaury de la Vieuville2013-06-081-2/+2
* Fix unused variable warning from my previous patch.JF Bastien2013-06-081-0/+1
* ARM FastISel integer sext/zext improvementsJF Bastien2013-06-071-38/+103
* Don't cache the instruction and register info from the TargetMachine, becauseBill Wendling2013-06-0715-42/+48
* ARM sched model: Use the right resources for DIVArnold Schwaighofer2013-06-071-1/+1
* ARM sched model: Add VFP div instruction on SwiftArnold Schwaighofer2013-06-071-0/+16
* ARM sched model: Add SIMD/VFP load/store instructions on SwiftArnold Schwaighofer2013-06-071-0/+364
* Revert "ARM sched model: Add SIMD/VFP load/store instructions on Swift"Arnold Schwaighofer2013-06-061-364/+0
* ARM sched model: Add SIMD/VFP load/store instructions on SwiftArnold Schwaighofer2013-06-061-0/+364
* ARM sched model: Add integer VFP/SIMD instructions on SwiftArnold Schwaighofer2013-06-063-0/+125
* ARM sched model: Add integer load/store instructions on SwiftArnold Schwaighofer2013-06-061-0/+209
* ARM sched model: Add integer arithmetic instructions on SwiftArnold Schwaighofer2013-06-061-0/+155
* ARM sched model: Cortex A9 - More InstRW sched resourcesArnold Schwaighofer2013-06-061-4/+45
* ARM sched model: Add branch thumb instructionsArnold Schwaighofer2013-06-061-18/+21
* ARM sched model: Add branch thumb2 instructionsArnold Schwaighofer2013-06-061-11/+15
* ARM sched model: Add branch instructionsArnold Schwaighofer2013-06-061-27/+35
* ARM sched model: Add preload thumb2 instructionsArnold Schwaighofer2013-06-061-3/+6
* ARM sched model: Add preload instructionsArnold Schwaighofer2013-06-061-2/+4
* ARM sched model: Add more ALU and CMP thumb instructionsArnold Schwaighofer2013-06-061-46/+61
* ARM sched model: Add more ALU and CMP thumb2 instructionsArnold Schwaighofer2013-06-061-52/+86
* Cache the TargetLowering info object as a pointer.Bill Wendling2013-06-062-17/+17
* ARM sched model: Add more ALU and CMP instructionsArnold Schwaighofer2013-06-051-37/+49
* ARM sched model: Add divsion, loads, branches, vfp cvtArnold Schwaighofer2013-06-054-7/+89
* ARMInstrInfo: Improve isSwiftFastImmShiftArnold Schwaighofer2013-06-051-0/+2
* This is a simple patch that changes RRX and RRXS to accept all registers as o...Mihai Popa2013-06-051-1/+1
* Cortex-R5 can issue Thumb2 integer division instructions.Evan Cheng2013-06-041-1/+2
* Revert series of sched model patches until I figure out what is going on.Arnold Schwaighofer2013-06-048-1277/+207
* ARM sched model: Add VFP div instruction on SwiftArnold Schwaighofer2013-06-041-0/+16
* ARM sched model: Add SIMD/VFP load/store instructions on SwiftArnold Schwaighofer2013-06-041-0/+364
* ARM sched model: Add integer VFP/SIMD instructions on SwiftArnold Schwaighofer2013-06-041-0/+120
* ARM sched model: Add integer load/store instructions on SwiftArnold Schwaighofer2013-06-041-0/+209
* ARM sched model: Add integer arithmetic instructions on SwiftArnold Schwaighofer2013-06-041-0/+155
* ARM sched model: Cortex A9 - More InstRW sched resourcesArnold Schwaighofer2013-06-041-4/+45
* ARM sched model: Add branch thumb instructionsArnold Schwaighofer2013-06-041-18/+21
* ARM sched model: Add branch thumb2 instructionsArnold Schwaighofer2013-06-041-11/+15
* ARM sched model: Add branch instructionsArnold Schwaighofer2013-06-041-27/+35
* ARM sched model: Add preload thumb2 instructionsArnold Schwaighofer2013-06-041-3/+6
* ARM sched model: Add preload instructionsArnold Schwaighofer2013-06-041-2/+4
* ARM sched model: Add more ALU and CMP thumb instructionsArnold Schwaighofer2013-06-041-46/+61
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