aboutsummaryrefslogtreecommitdiffstats
path: root/lib/Target/ARM
Commit message (Expand)AuthorAgeFilesLines
* Prune includes and replace uses of ARMRegisterInfo.h with ARMBaeRegisterInfo.hCraig Topper2012-03-267-10/+2
* Replace uses of ARMBaseInstrInfo and ARMTargetMachine with the Base versions.Craig Topper2012-03-258-18/+12
* Prune some includes and forward declarations.Craig Topper2012-03-251-0/+1
* ARM tidy up ARMConstantIsland.cpp.Jim Grosbach2012-03-231-156/+158
* Added soft fail checks for the disassembler when decoding some corner cases o...Silviu Baranga2012-03-221-1/+81
* Added soft fail cases for the disassembler when decoding LDRSBT, LDRHT or LDR...Silviu Baranga2012-03-222-5/+35
* Added soft fail cases for the disassembler when decoding MUL instructions on ...Silviu Baranga2012-03-221-5/+6
* Fix ARM disassembly of VST1 and VST2 instructions with writeback. And add testKevin Enderby2012-03-211-0/+19
* Change conditional instructions definitions, e.g. ANDCC, ARMPseudoExpand and ...Evan Cheng2012-03-202-96/+56
* remove unused variableMatt Beaumont-Gay2012-03-201-1/+0
* Require a base pointer for stack realignment when SP may vary dynamically.Bob Wilson2012-03-201-2/+3
* Remove some redundant checks.Bob Wilson2012-03-202-3/+2
* Fix assembling ARM vst2 instructions with double-spaced registers.Kevin Enderby2012-03-201-1/+1
* ARM non-scattered MachO relocations for movw/movt.Jim Grosbach2012-03-201-22/+58
* The ARM instructions that have an unpredictable behavior when the pc register...Silviu Baranga2012-03-202-4/+10
* Test Commit - add a newlineRichard Barton2012-03-201-0/+1
* ARM branch relaxation for unconditional t1 branches.Jim Grosbach2012-03-191-0/+11
* ARM assembly, accept optional '#' on lane index number.Jim Grosbach2012-03-191-0/+6
* Perform mul combine when multiplying wiht negative constants.Anton Korobeynikov2012-03-191-18/+48
* Reorder includes to match coding standards. Fix an issue or two exposed by that.Craig Topper2012-03-1718-29/+20
* Check if we can handle the arguments of a call (and therefore the call) inBill Wendling2012-03-161-8/+52
* ARM fix silly typo in optional operand alias.Jim Grosbach2012-03-161-1/+1
* ARM divided syntax fmrx/fmxr mnemonics.Jim Grosbach2012-03-161-0/+2
* ARM ldm/stm register lists can be out of order.Jim Grosbach2012-03-161-2/+6
* ARM optional operand on MRC/MCR assembly instructions.Jim Grosbach2012-03-162-0/+24
* ARM vmrs system registers mvfr0 and mvfr1 handling.Jim Grosbach2012-03-162-0/+6
* Remove inadvertant commit.Jim Grosbach2012-03-151-23/+0
* [fast-isel] Address Eli's comments for r152847. Specifically, add a test caseChad Rosier2012-03-151-9/+8
* [fast-isel] Don't try to encode LONG_MIN using cmn instructions.Chad Rosier2012-03-151-5/+9
* ARM case-insensitive checking for APSR_nzcv.Jim Grosbach2012-03-153-4/+29
* ARM aliases for pre-unified syntax fcmpz[sd] mnemonics.Jim Grosbach2012-03-152-1/+6
* Use vmov.f32 to materialize f32 consts on ARM. This relaxes constraints onLang Hames2012-03-152-0/+26
* Fix VCVT decoding (between floating-point and fixed-point, Floating-point). ...Kristof Beyls2012-03-151-16/+38
* Switch to unified syntax for VFP instructions in inline assembly.Bob Wilson2012-03-121-2/+2
* Convert more static tables of registers used by calling convention to uint16_...Craig Topper2012-03-112-7/+7
* Use uint16_t to store registers and opcode in static tables in the target spe...Craig Topper2012-03-113-12/+12
* Use uint16_t to store instruction implicit uses and defs. Reduces static data.Craig Topper2012-03-081-1/+1
* ARM don't use MCRelaxAll, as it's not safe on ARM.Jim Grosbach2012-03-081-2/+2
* [fast-isel] ARMEmitCmp generates FMSTAT, which transfers the floating-point Chad Rosier2012-03-071-4/+2
* ARM pre-v6 assembly parsing for umull/smull.Jim Grosbach2012-03-071-0/+10
* ARM pre-v6 alias for 'nop' to 'mov r0, r0'Jim Grosbach2012-03-071-0/+4
* Tidy up. Remove dead code that slipped into previous commit.Jim Grosbach2012-03-071-6/+0
* ARM more NEON VLD/VST composite physical register refactoring.Jim Grosbach2012-03-065-39/+58
* ARM refactor more NEON VLD/VST instructions to use composite physregsJim Grosbach2012-03-068-168/+117
* Tidy up. Kill some dead code.Jim Grosbach2012-03-062-10/+0
* Allow the same types in DPair as in QPR.Jakob Stoklund Olesen2012-03-061-1/+2
* Fix a bug in the ARM disassembly of the neon VLD2 all lanes instruction.Kevin Enderby2012-03-061-7/+7
* Add <imp-def> operands when reloading into physregs.Jakob Stoklund Olesen2012-03-061-0/+4
* Split fpscr into two registers: FPSCR and FPSCR_NZCV.Lang Hames2012-03-064-11/+17
* ARM vpush/vpop assembler mnemonics accept an optional size suffix.Jim Grosbach2012-03-051-0/+8