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* Added support for generate DWARF .debug_aranges sections automatically.Richard Mitton2013-09-191-1/+1
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191052 91177308-0d34-0410-b5e6-96231b3b80d8
* [ARMv8] Add support for the v8 cryptography extensions.Amara Emerson2013-09-198-16/+142
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@190996 91177308-0d34-0410-b5e6-96231b3b80d8
* [ARMv8] Add CRC instructions.Joey Gouly2013-09-183-1/+80
| | | | | | | Patch by Bradley Smith! git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@190928 91177308-0d34-0410-b5e6-96231b3b80d8
* [ARM] Fix the deprecation of MCR encodings that map to CP15{ISB,DSB,DMB}.Joey Gouly2013-09-172-9/+27
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@190862 91177308-0d34-0410-b5e6-96231b3b80d8
* ARM: Deduplicate ConstantPoolValues.Benjamin Kramer2013-09-162-47/+36
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@190779 91177308-0d34-0410-b5e6-96231b3b80d8
* Replace some unnecessary vector copies with references.Benjamin Kramer2013-09-151-3/+3
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@190770 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix spelling.Robert Wilhelm2013-09-141-1/+1
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@190749 91177308-0d34-0410-b5e6-96231b3b80d8
* [ARMv8] Change hasV8Fp to hasFPARMv8, and other command line optionsJoey Gouly2013-09-138-31/+31
| | | | | | | | to be more consistent. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@190692 91177308-0d34-0410-b5e6-96231b3b80d8
* [ARMv8] Emit the proper .fpu directive.Joey Gouly2013-09-131-3/+6
| | | | | | | Patch by Bradley Smith! git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@190683 91177308-0d34-0410-b5e6-96231b3b80d8
* Add an instruction deprecation feature to TableGen.Joey Gouly2013-09-123-31/+27
| | | | | | | | | | | | | | | | | | | | | | | | The 'Deprecated' class allows you to specify a SubtargetFeature that the instruction is deprecated on. The 'ComplexDeprecationPredicate' class allows you to define a custom predicate that is called to check for deprecation. For example: ComplexDeprecationPredicate<"MCR"> would mean you would have to define the following function: bool getMCRDeprecationInfo(MCInst &MI, MCSubtargetInfo &STI, std::string &Info) Which returns 'false' for not deprecated, and 'true' for deprecated and store the warning message in 'Info'. The MCTargetAsmParser constructor was chaned to take an extra argument of the MCInstrInfo class, so out-of-tree targets will need to be changed. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@190598 91177308-0d34-0410-b5e6-96231b3b80d8
* ARM: Use the PICADD opcode calculated.Jim Grosbach2013-09-101-2/+6
| | | | | | | | | | | | | | We were figuring out whether to use tPICADD or PICADD, then just using tPICADD unconditionally anyway. Oops. A testcase from someone familiar enough with ELF to produce one would be appreciated. The existing PIC testcase correctly verifies the .s generated, but that doesn't catch this bug, which only showed up in direct-to-object mode. http://llvm.org/bugs/show_bug.cgi?id=17180 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@190417 91177308-0d34-0410-b5e6-96231b3b80d8
* Remove unused private member in ARMAsmPrinter.cpp.Logan Chien2013-09-101-1/+1
| | | | | | | | | This commit removes the unused "AttributeItem" from ObjectAttributeEmitter. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@190412 91177308-0d34-0410-b5e6-96231b3b80d8
* [ARMv8] Prevent generation of deprecated IT blocks on ARMv8 in Thumb mode.Joey Gouly2013-09-094-36/+121
| | | | | | | | | | IT blocks can only be one instruction lonf, and can only contain a subset of the 16 instructions. Patch by Artyom Skrobov! git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@190309 91177308-0d34-0410-b5e6-96231b3b80d8
* Generate compact unwind encoding from CFI directives.Bill Wendling2013-09-092-2/+5
| | | | | | | | | | | | | | | | We used to generate the compact unwind encoding from the machine instructions. However, this had the problem that if the user used `-save-temps' or compiled their hand-written `.s' file (with CFI directives), we wouldn't generate the compact unwind encoding. Move the algorithm that generates the compact unwind encoding into the MCAsmBackend. This way we can generate the encoding whether the code is from a `.ll' or `.s' file. <rdar://problem/13623355> git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@190290 91177308-0d34-0410-b5e6-96231b3b80d8
* [ARMv8] Implement the new DMB/DSB operands.Joey Gouly2013-09-057-20/+27
| | | | | | | | | This removes the custom ISD Node: MEMBARRIER and replaces it with an intrinsic. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@190055 91177308-0d34-0410-b5e6-96231b3b80d8
* Add AArch32 DCPS{1,2,3} and HLT instructions.Richard Barton2013-09-054-7/+47
| | | | | | | | | | | | | | | | | | | These were pretty straightforward instructions, with some assembly support required for HLT. The ARM assembler is keen to split the instruction mnemonic into a (non-existent) 'H' instruction with the LT condition code. An exception for HLT is needed. HLT follows the same rules as BKPT when in IT blocks, so the special BKPT hadling code has been adapted to handle HLT also. Regression tests added including diagnostic tests for out of range immediates and illegal condition codes, as well as negative tests for pre-ARMv8. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@190053 91177308-0d34-0410-b5e6-96231b3b80d8
* Reverting 190043 for now.Tilmann Scheller2013-09-053-23/+3
| | | | | | | | | Solution is not sufficient to prevent 'mov pc, lr' being emitted for jump table code. Test case doesn't trigger the added functionality. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@190047 91177308-0d34-0410-b5e6-96231b3b80d8
* ARM: Add GPR register class excluding LR for use with the ADR instruction.Tilmann Scheller2013-09-053-3/+23
| | | | | | | | | | This improves code generation for jump tables by avoiding the emission of "mov pc, lr" which could fool the processor into believing this is a return from a function causing mispredicts. The code generation logic for jump tables uses ADR to materialize the address of the jump target. Patch by Daniel Stewart! git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@190043 91177308-0d34-0410-b5e6-96231b3b80d8
* ARM: Teach A15 SDOptimizer to properly handle D-reg by-lane.Jim Grosbach2013-09-041-0/+7
| | | | | | | | | | | | | | These instructions, such as vmul.f32, require the second source operand to be in D0-D15 rather than the full D0-D31. When optimizing, make sure to account for that by constraining the register class of a replacement virtual register to be compatible with the virtual register(s) it's replacing. I've been unsuccessful in creating a non-fragile regression test. This issue was detected by the LLVM nightly test suite running on an A15 (Bullet). PR17093: http://llvm.org/bugs/show_bug.cgi?id=17093 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@189972 91177308-0d34-0410-b5e6-96231b3b80d8
* Swift: Only build vldm/vstm with q register aligned register listsArnold Schwaighofer2013-09-041-1/+4
| | | | | | | | Unaligned vldm/vstm need more uops and therefore are slower in general on swift. radar://14522102 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@189961 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix scheduling for vldm/vstm instructions that load/store more than 32 bytes ↵Silviu Baranga2013-09-041-78/+54
| | | | | | on Cortex-A9. This also makes the existing code more compact. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@189958 91177308-0d34-0410-b5e6-96231b3b80d8
* Revert "Revert "ARM: Improve pattern for isel mul of vector by scalar.""Jim Grosbach2013-09-031-0/+11
| | | | | | | | | This reverts commit r189648. Fixes for the previously failing clang-side arm_neon_intrinsics test cases will be checked in separately. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@189841 91177308-0d34-0410-b5e6-96231b3b80d8
* ARM: Default to the Swift CPU when targeting armv7s/thumbv7s.Tilmann Scheller2013-09-021-2/+7
| | | | | | | | | | Test cases adjusted accordingly. This fixes rdar://14871821. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@189766 91177308-0d34-0410-b5e6-96231b3b80d8
* Revert 189756 for now, it doesn't match what rdar://14871821 really wants.Tilmann Scheller2013-09-021-7/+2
| | | | | | | What we really want is to enable Swift by default for *v7s triples (and there already seems to be some logic which attempts to do that). In that case the iOS version doesn't matter. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@189763 91177308-0d34-0410-b5e6-96231b3b80d8
* ARM: Default to Swift when compiling for iOS 6 or later.Tilmann Scheller2013-09-021-2/+7
| | | | | | | | | | Test cases adjusted accordingly. This fixes rdar://14871821. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@189756 91177308-0d34-0410-b5e6-96231b3b80d8
* Move everything depending on Object/MachOFormat.h over to Support/MachO.h.Charles Davis2013-09-012-81/+80
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@189728 91177308-0d34-0410-b5e6-96231b3b80d8
* Revert "ARM: Improve pattern for isel mul of vector by scalar."Michael Gottesman2013-08-301-11/+0
| | | | | | | | This reverts commit r189619. The commit was breaking the arm_neon_intrinsic test. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@189648 91177308-0d34-0410-b5e6-96231b3b80d8
* ARM: Improve pattern for isel mul of vector by scalar.Jim Grosbach2013-08-291-0/+11
| | | | | | | | | | | In addition to recognizing when the multiply's second argument is coming from an explicit VDUPLANE, also look for a plain scalar f32 reference and reference it via the corresponding vector lane. rdar://14870054 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@189619 91177308-0d34-0410-b5e6-96231b3b80d8
* Clean up some usage of Triple. The base class has methods for determining ↵Cameron Esfahani2013-08-293-6/+5
| | | | | | if the target is iOS and Linux. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@189604 91177308-0d34-0410-b5e6-96231b3b80d8
* [ARMv8]Joey Gouly2013-08-282-14/+20
| | | | | | | | | | | | Fix a few things in one swoop. # Add some negative tests. # Fix some formatting issues. # Add some missing IsThumb / ARMv8 # Fix some outs / ins mistakes. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@189490 91177308-0d34-0410-b5e6-96231b3b80d8
* ARM: Use "dmb sy" for barriers on M-class CPUsTim Northover2013-08-281-1/+4
| | | | | | | | The usual default of "dmb ish" (inner-shareable) isn't even a valid instruction on v6M or v7M (well, it does the same thing but software is strongly discouraged from using it) so we should emit a full-system barrier there. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@189483 91177308-0d34-0410-b5e6-96231b3b80d8
* [ARMv8] Add a missing IsThumb to t2LDAEXD.Joey Gouly2013-08-281-1/+1
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@189482 91177308-0d34-0410-b5e6-96231b3b80d8
* ARM: remove unused v(add|sub)hn and vqdml[as]l intrinsics.Tim Northover2013-08-281-8/+6
| | | | | | | Clang is now generating cleaner IR, so this removes the old variants which should be completely unused. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@189481 91177308-0d34-0410-b5e6-96231b3b80d8
* ARM: add patterns for vqdmlal with separate vqdmull and vqaddsTim Northover2013-08-281-0/+38
| | | | | | | | | The vqdmlal and vqdmlls instructions are really just a fused pair consisting of a vqdmull.sN and a vqadd.sN. This adds patterns to LLVM so that we can switch Clang's CodeGen over to generating these instead of the special vqdmlal intrinsics. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@189480 91177308-0d34-0410-b5e6-96231b3b80d8
* [ARMv8] Add MC support for the new load/store acquire/release instructions.Joey Gouly2013-08-275-27/+218
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@189388 91177308-0d34-0410-b5e6-96231b3b80d8
* [ARMv8] Add some negative tests for the recent VFP/NEON instructions.Joey Gouly2013-08-272-2/+7
| | | | | | | Fix two issues I found while writing these tests. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@189341 91177308-0d34-0410-b5e6-96231b3b80d8
* ARM: add natural patterns for vaddhl and vsubhl.Tim Northover2013-08-271-0/+14
| | | | | | | | These instructions aren't particularly complicated and it's well worth having patterns for some reasonably useful LLVM IR that will match them. Soon we should be able to switch Clang over to producing this natural version. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@189335 91177308-0d34-0410-b5e6-96231b3b80d8
* Revert "Fix the build broken by r189315." and "Move everything depending on ↵Charles Davis2013-08-272-79/+81
| | | | | | | | | Object/MachOFormat.h over to Support/MachO.h." This reverts commits r189319 and r189315. r189315 broke some tests on what I believe are big-endian platforms. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@189321 91177308-0d34-0410-b5e6-96231b3b80d8
* Move everything depending on Object/MachOFormat.h over to Support/MachO.h.Charles Davis2013-08-272-81/+79
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@189315 91177308-0d34-0410-b5e6-96231b3b80d8
* ARM: Constrain regclass for TSTri instruction.Jim Grosbach2013-08-261-0/+2
| | | | | | | | | Get the register class right for the TST instruction. This keeps the machine verifier happy, enabling us to turn it on for another test. rdar://12594152 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@189274 91177308-0d34-0410-b5e6-96231b3b80d8
* ARM: FastISel verifier error cleanup.Jim Grosbach2013-08-261-0/+7
| | | | | | | | | Constant pool and global value reference instructions need more restricted register classes than plain GPR. rdar://12594152 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@189270 91177308-0d34-0410-b5e6-96231b3b80d8
* ARM: Fix ELF global base reg intialization.Jim Grosbach2013-08-261-3/+8
| | | | | | | | | | | | | | | | | | The create machine code wasn't properly in SSA, which the machine verifier properly complains about. Now that fast-isel is closer to verifier clean, errors like this show up more clearly. Additionally, the Thumb pseudo tPICADD was used for both ARM and Thumb mode functions, which is obviously wrong. Fix that along the way. Test case is part of the following commit which will finish making an additional fast-isel test verifier clean an enable it for the regression test suite. This commit is separate since its not just a verifier cleanup, but an actual correctness issue. rdar://12594152 (for the fast-isel verifier aspects) git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@189269 91177308-0d34-0410-b5e6-96231b3b80d8
* [ARM] Fix another ARM FastISel -verify-machineinstrs issue.Joey Gouly2013-08-231-0/+4
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@189109 91177308-0d34-0410-b5e6-96231b3b80d8
* [ARMv8] Add CodeGen for VMAXNM/VMINNM.Joey Gouly2013-08-234-6/+31
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@189103 91177308-0d34-0410-b5e6-96231b3b80d8
* ARM: make sure ARM-mode pseudo-inst requires IsARMTim Northover2013-08-231-1/+1
| | | | | | | | | | I'd forgotten that "Requires" blocks override rather than add to the constraints, so my pseudo-instruction was being selected in Thumb mode leading to nonsense instructions. rdar://problem/14817358 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@189096 91177308-0d34-0410-b5e6-96231b3b80d8
* [ARMv8] Add CodeGen support for VSEL.Joey Gouly2013-08-222-9/+105
| | | | | | | | | This uses the ARMcmov pattern that Tim cleaned up in r188995. Thanks to Simon Tatham for his floating point help! git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@189024 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix ARM vcvt encoding when the number of fractional bits is zero.Mihai Popa2013-08-221-0/+19
| | | | | | | | | | | | | The instruction to convert between floating point and fixed point representations takes an immediate operand for the number of fractional bits of the fixed point value. ARMARM specifies that when that number of bits is zero, the assembler should encode floating point/integer conversion instructions. This patch adds the necessary instruction aliases to achieve this behaviour. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@189009 91177308-0d34-0410-b5e6-96231b3b80d8
* [ARM] Constrain some register classes in EmitAtomicBinary64 so thatJoey Gouly2013-08-221-0/+4
| | | | | | | we pass these tests with -verify-machineinstrs. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@189006 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix ARM FastISel PIC function call.Logan Chien2013-08-221-2/+9
| | | | | | | | The function call to external function should come with PLT relocation type if the PIC relocation model is used. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@189002 91177308-0d34-0410-b5e6-96231b3b80d8
* ARM: use TableGen patterns to select CMOV operations.Tim Northover2013-08-227-326/+137
| | | | | | | | | | | | Back in the mists of time (2008), it seems TableGen couldn't handle the patterns necessary to match ARM's CMOV node that we convert select operations to, so we wrote a lot of fairly hairy C++ to do it for us. TableGen can deal with it now: there were a few minor differences to CodeGen (see tests), but nothing obviously worse that I could see, so we should probably address anything that *does* come up in a localised manner. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@188995 91177308-0d34-0410-b5e6-96231b3b80d8
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