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* Remove the isMoveInstr() hook.Jakob Stoklund Olesen2010-07-162-48/+0
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108567 91177308-0d34-0410-b5e6-96231b3b80d8
* Use a small local function for a single remaining late isMoveInstr call inJakob Stoklund Olesen2010-07-161-24/+42
| | | | | | Thumb2ITBlockPass. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108564 91177308-0d34-0410-b5e6-96231b3b80d8
* Rename DBG_LABEL PROLOG_LABEL, because it's only used during prolog emission andBill Wendling2010-07-162-2/+2
| | | | | | | thus is a much more meaningful name. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108563 91177308-0d34-0410-b5e6-96231b3b80d8
* Split -enable-finite-only-fp-math to two options:Evan Cheng2010-07-152-4/+5
| | | | | | | -enable-no-nans-fp-math and -enable-no-infs-fp-math. All of the current codegen fp math optimizations only care whether the fp arithmetics arguments and results can never be NaN. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108465 91177308-0d34-0410-b5e6-96231b3b80d8
* Random note about bswap.Eli Friedman2010-07-151-0/+26
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108396 91177308-0d34-0410-b5e6-96231b3b80d8
* Remove restriction on NEON alignment values. Some of the NEON ld/stBob Wilson2010-07-143-9/+4
| | | | | | | | instructions use different values (e.g., 2-byte or 4-byte alignment). Also fix ARMInstPrinter to print these alignments as bits instead of bytes. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108386 91177308-0d34-0410-b5e6-96231b3b80d8
* Don't pass StringRef by reference.Benjamin Kramer2010-07-141-7/+7
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108366 91177308-0d34-0410-b5e6-96231b3b80d8
* Improve 64-subtraction of immediates when parts of the immediate can fitJim Grosbach2010-07-142-11/+40
| | | | | | | | | | | | | in the literal field of an instruction. E.g., long long foo(long long a) { return a - 734439407618LL; } rdar://7038284 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108339 91177308-0d34-0410-b5e6-96231b3b80d8
* Add missing address register update to t2LDM_RET instruction.Bob Wilson2010-07-141-1/+1
| | | | | | | Patch by Brian Lucas. PR7636. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108332 91177308-0d34-0410-b5e6-96231b3b80d8
* A couple potential optimizations inspired by comment 4 in PR6773.Eli Friedman2010-07-141-0/+41
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108328 91177308-0d34-0410-b5e6-96231b3b80d8
* Add support for NEON VMVN immediate instructions.Bob Wilson2010-07-143-7/+48
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108324 91177308-0d34-0410-b5e6-96231b3b80d8
* The bits in the cmode field of 32-bit VMOV immediate instructions all dependBob Wilson2010-07-141-2/+2
| | | | | | | of the value of the immediate. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108323 91177308-0d34-0410-b5e6-96231b3b80d8
* Add an ARM-specific DAG combining to avoid redundant VDUPLANE nodes.Bob Wilson2010-07-141-0/+29
| | | | | | | Radar 7373643. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108303 91177308-0d34-0410-b5e6-96231b3b80d8
* Use a target-specific VMOVIMM DAG node instead of BUILD_VECTOR to representBob Wilson2010-07-133-192/+78
| | | | | | | NEON VMOV-immediate instructions. This simplifies some things. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108275 91177308-0d34-0410-b5e6-96231b3b80d8
* Extend the r107852 optimization which turns some fp compare to code sequence ↵Evan Cheng2010-07-133-71/+240
| | | | | | using only i32 operations. It now optimize some f64 compares when fp compare is exceptionally slow (e.g. cortex-a8). It also catches comparison against 0.0. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108258 91177308-0d34-0410-b5e6-96231b3b80d8
* Add an ARM "feature". Cortex-a8 fp comparison is very slow (> 20 cycles).Evan Cheng2010-07-132-1/+7
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108256 91177308-0d34-0410-b5e6-96231b3b80d8
* Move NEON "modified immediate" encode/decode into ARMAddressingModes.h toBob Wilson2010-07-134-77/+84
| | | | | | | avoid replicated code. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108227 91177308-0d34-0410-b5e6-96231b3b80d8
* Remove some code that doesn't appear to do anything. All the ARM callBob Wilson2010-07-121-5/+0
| | | | | | | | | instructions already have implicit defs of LR. The comment suggests that this is intended to fix something like pr6111, but it doesn't really do that either. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108186 91177308-0d34-0410-b5e6-96231b3b80d8
* Convert some tab stops into spaces.Duncan Sands2010-07-123-8/+8
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108130 91177308-0d34-0410-b5e6-96231b3b80d8
* RISC architectures get their memory operand folding for free.Jakob Stoklund Olesen2010-07-114-320/+0
| | | | | | | | The only folding these load/store architectures can do is converting COPY into a load or store, and the target independent part of foldMemoryOperand already knows how to do that. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108099 91177308-0d34-0410-b5e6-96231b3b80d8
* Make getPhysicalRegisterRegClass non-virtual. Should be able to remove it soon.Rafael Espindola2010-07-112-18/+0
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108094 91177308-0d34-0410-b5e6-96231b3b80d8
* Replace copyRegToReg with copyPhysReg for ARM.Jakob Stoklund Olesen2010-07-116-146/+84
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108078 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix va_arg for doubles. With this patch VAARG nodes always contain theRafael Espindola2010-07-111-0/+4
| | | | | | | | | | | | | | | correct alignment information, which simplifies ExpandRes_VAARG a bit. The patch introduces a new alignment information to TargetLoweringInfo. This is needed since the two natural candidates cannot be used: * The 's' in target data: If this is set to the minimal alignment of any argument, getCallFrameTypeAlignment would return 4 for doubles on ARM for example. * The getTransientStackAlignment method. It is possible for an architecture to have argument less aligned than what we maintain the stack pointer. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108072 91177308-0d34-0410-b5e6-96231b3b80d8
* Add parentheses yet again to satisfy GCC's warnings.Chandler Carruth2010-07-101-3/+3
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108043 91177308-0d34-0410-b5e6-96231b3b80d8
* Automatically fold COPY instructions into stack load/store.Jakob Stoklund Olesen2010-07-091-1/+1
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108012 91177308-0d34-0410-b5e6-96231b3b80d8
* In the presence of variable sized objects, allocate an emergency spill slot.Jim Grosbach2010-07-091-3/+10
| | | | | | rdar://8131327 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108008 91177308-0d34-0410-b5e6-96231b3b80d8
* Print "dregpair" NEON operands with a space between them, for readability andBob Wilson2010-07-091-1/+1
| | | | | | | consistency with other instructions that have lists of register operands. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107944 91177308-0d34-0410-b5e6-96231b3b80d8
* Check for FiniteOnlyFPMath as well.Evan Cheng2010-07-081-1/+1
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107904 91177308-0d34-0410-b5e6-96231b3b80d8
* The NEONPreAllocPass should never have to assign fixed registers anymore.Bob Wilson2010-07-081-34/+1
| | | | | | | This pass can go away entirely soon. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107892 91177308-0d34-0410-b5e6-96231b3b80d8
* For big-endian systems, VLD2/VST2 with 32-bit vector elements will swap theBob Wilson2010-07-081-2/+2
| | | | | | | | words within the 64-bit D registers. Use VLD1/VST1 with 64-bit elements instead. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107890 91177308-0d34-0410-b5e6-96231b3b80d8
* Clean up a comment.Bob Wilson2010-07-081-5/+5
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107882 91177308-0d34-0410-b5e6-96231b3b80d8
* Convert EXTRACT_SUBREG to COPY when emitting machine instrs.Jakob Stoklund Olesen2010-07-081-3/+3
| | | | | | | | | EXTRACT_SUBREG no longer appears as a machine instruction. Use COPY instead. Add isCopy() checks in many places using isMoveInstr() and isExtractSubreg(). The isMoveInstr hook will be removed later. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107879 91177308-0d34-0410-b5e6-96231b3b80d8
* r107852 is only safe with -enable-unsafe-fp-math to account for +0.0 == -0.0.Evan Cheng2010-07-081-3/+5
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107856 91177308-0d34-0410-b5e6-96231b3b80d8
* Optimize some vfp comparisons to integer ones. This patch implements the ↵Evan Cheng2010-07-082-10/+48
| | | | | | | | | | | | | | | | | | | | | | | | | simplest case when the following conditions are met: 1. The arguments are f32. 2. The arguments are loads and they have no uses other than the comparison. 3. The comparison code is EQ or NE. e.g. vldr.32 s0, [r1] vldr.32 s1, [r0] vcmpe.f32 s1, s0 vmrs apsr_nzcv, fpscr beq LBB0_2 => ldr r1, [r1] ldr r0, [r0] cmp r0, r1 beq LBB0_2 More complicated cases will be implemented in subsequent patches. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107852 91177308-0d34-0410-b5e6-96231b3b80d8
* Changes to ARM tail calls, mostly cosmetic.Dale Johannesen2010-07-083-8/+20
| | | | | | | | | | | Add explicit testcases for tail calls within the same module. Duplicate some code to humor those who think .w doesn't apply on ARM. Leave this disabled on Thumb1, and add some comments explaining why it's hard and won't gain much. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107851 91177308-0d34-0410-b5e6-96231b3b80d8
* grammarJim Grosbach2010-07-071-1/+1
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107831 91177308-0d34-0410-b5e6-96231b3b80d8
* Handle cases where the post-RA scheduler may move instructions between theJim Grosbach2010-07-071-6/+21
| | | | | | | | | | | address calculation instructions leading up to a jump table when we're trying to convert them into a TB[H] instruction in Thumb2. This realistically shouldn't happen much, if at all, for well formed inputs, but it's more correct to handle it. rdar://7387682 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107830 91177308-0d34-0410-b5e6-96231b3b80d8
* grammar and trailing whitespaceJim Grosbach2010-07-071-6/+6
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107811 91177308-0d34-0410-b5e6-96231b3b80d8
* Split the SDValue out of OutputArg so that SelectionDAG-independentDan Gohman2010-07-072-4/+10
| | | | | | | code can do calling-convention queries. This obviates OutputArgReg. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107786 91177308-0d34-0410-b5e6-96231b3b80d8
* Also use REG_SEQUENCE for VTBX instructions.Bob Wilson2010-07-072-24/+30
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107743 91177308-0d34-0410-b5e6-96231b3b80d8
* Mark eh.sjlj.set/longjmp custom lowerings as Darwin-only since that's whereJim Grosbach2010-07-071-2/+4
| | | | | | they've been tested to work. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107742 91177308-0d34-0410-b5e6-96231b3b80d8
* By default, the eh.sjlj.setjmp/longjmp intrinsics should just do nothing ratherJim Grosbach2010-07-061-0/+2
| | | | | | | | | than assuming a target will custom lower them. Targets which do so should exlicitly mark them as having custom lowerings. PR7454. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107734 91177308-0d34-0410-b5e6-96231b3b80d8
* Use REG_SEQUENCE nodes to make the table registers for VTBL instructions beBob Wilson2010-07-062-10/+61
| | | | | | | allocated to consecutive registers. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107730 91177308-0d34-0410-b5e6-96231b3b80d8
* Track defs for all aliases in NEONMoveFix.Jakob Stoklund Olesen2010-07-061-2/+2
| | | | | | | This means that an instruction defining an S register will affect the domain of the parent D register. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107725 91177308-0d34-0410-b5e6-96231b3b80d8
* Propagate debug loc.Devang Patel2010-07-061-2/+2
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107710 91177308-0d34-0410-b5e6-96231b3b80d8
* Represent NEON load/store alignments in bytes, not bits.Bob Wilson2010-07-063-7/+13
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107701 91177308-0d34-0410-b5e6-96231b3b80d8
* Reapply r107655 with fixes; insert the pseudo instruction intoDan Gohman2010-07-061-21/+31
| | | | | | | | the block before calling the expansion hook. And don't put EFLAGS in a mbb's live-in list twice. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107691 91177308-0d34-0410-b5e6-96231b3b80d8
* Don't create neon moves in CopyRegToReg. NEONMoveFixPass will do the conversionRafael Espindola2010-07-061-4/+6
| | | | | | if profitable. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107673 91177308-0d34-0410-b5e6-96231b3b80d8
* Revert r107655.Dan Gohman2010-07-061-31/+21
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107668 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix a bunch of custom-inserter functions to handle the case whereDan Gohman2010-07-061-21/+31
| | | | | | | the pseudo instruction is not at the end of the block. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107655 91177308-0d34-0410-b5e6-96231b3b80d8
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