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* [ARM] Fix FP ABI attributes with no VFP enabled.Amara Emerson2013-10-111-14/+12
* ARM: Put isV8EligibleForIT into the llvm namespace. While there make it inline.Benjamin Kramer2013-10-101-2/+4
* ARM: correct liveness flags during ARMLoadStoreOptTim Northover2013-10-101-0/+77
* Flip the ownership of MCStreamer and MCTargetStreamer.Benjamin Kramer2013-10-091-1/+1
* Add a MCTargetStreamer interface.Rafael Espindola2013-10-085-58/+186
* Struct byval: use the correct alignment for loads generated to loadManman Ren2013-10-071-1/+2
* [ARM] Improve build attributes emission.Amara Emerson2013-10-076-56/+91
* Remove getEHExceptionRegister and getEHHandlerRegister.Rafael Espindola2013-10-072-12/+0
* ARM: allow cortex-m0 to use hint instructionsTim Northover2013-10-075-9/+22
* Remove some really nasty uses of hasRawTextSupport.Rafael Espindola2013-10-055-47/+8
* ARM: optimizeSelect has to consider the previous register classMatthias Braun2013-10-041-4/+9
* ARM: do not add a regmask for TAILJUMPsMatthias Braun2013-10-041-16/+18
* ARM: preserve undef flag in pseudo instruction expandersMatthias Braun2013-10-041-19/+14
* [ARM] Warn on deprecated IT blocks in v8 AArch32 assembly.Amara Emerson2013-10-037-78/+126
* ARM: support interrupt attributeTim Northover2013-10-018-21/+148
* [ARM] Remove an unused function from the disassembler.Joey Gouly2013-10-011-11/+0
* [ARM] Introduce the 'sevl' instruction in ARMv8.Joey Gouly2013-10-015-29/+22
* [ARM] Clean up ARMAsmParser::validateInstruction().Tilmann Scheller2013-09-301-38/+36
* [ARM] Assembler: ARM LDRD with writeback requires the base register to be dif...Tilmann Scheller2013-09-301-4/+19
* Swift model: Fix uop description on some writesArnold Schwaighofer2013-09-301-2/+11
* IfConverter: Use TargetSchedule for instruction latenciesArnold Schwaighofer2013-09-302-0/+20
* Even more spelling fixes for "instruction".Robert Wilhelm2013-09-282-2/+2
* ARM: Teach assembler to enforce constraints for ARM LDRD destination register...Tilmann Scheller2013-09-271-1/+10
* Fix comment.Tilmann Scheller2013-09-271-1/+1
* ARM: Teach assembler to enforce constraint for Thumb2 LDRD (literal/immediate...Tilmann Scheller2013-09-271-0/+11
* Fix PR 17372: Emitting PLD for stack address for ARM Thumb2Weiming Zhao2013-09-261-0/+7
* [ARM] Use the load-acquire/store-release instructions optimally in AArch32.Amara Emerson2013-09-266-305/+495
* Fix PR 17368: disable vector mul distribution for square of add/sub for ARMWeiming Zhao2013-09-251-0/+10
* CriticalAntiDepBreaker is no longer needed for armv7 scheduling.Andrew Trick2013-09-251-3/+1
* [ARM] Split A/R class into separate subtarget features.Amara Emerson2013-09-235-23/+37
* ISelDAG: spot chain cycles involving MachineNodesTim Northover2013-09-221-1/+3
* Added support for generate DWARF .debug_aranges sections automatically.Richard Mitton2013-09-191-1/+1
* [ARMv8] Add support for the v8 cryptography extensions.Amara Emerson2013-09-198-16/+142
* [ARMv8] Add CRC instructions.Joey Gouly2013-09-183-1/+80
* [ARM] Fix the deprecation of MCR encodings that map to CP15{ISB,DSB,DMB}.Joey Gouly2013-09-172-9/+27
* ARM: Deduplicate ConstantPoolValues.Benjamin Kramer2013-09-162-47/+36
* Replace some unnecessary vector copies with references.Benjamin Kramer2013-09-151-3/+3
* Fix spelling.Robert Wilhelm2013-09-141-1/+1
* [ARMv8] Change hasV8Fp to hasFPARMv8, and other command line optionsJoey Gouly2013-09-138-31/+31
* [ARMv8] Emit the proper .fpu directive.Joey Gouly2013-09-131-3/+6
* Add an instruction deprecation feature to TableGen.Joey Gouly2013-09-123-31/+27
* ARM: Use the PICADD opcode calculated.Jim Grosbach2013-09-101-2/+6
* Remove unused private member in ARMAsmPrinter.cpp.Logan Chien2013-09-101-1/+1
* [ARMv8] Prevent generation of deprecated IT blocks on ARMv8 in Thumb mode.Joey Gouly2013-09-094-36/+121
* Generate compact unwind encoding from CFI directives.Bill Wendling2013-09-092-2/+5
* [ARMv8] Implement the new DMB/DSB operands.Joey Gouly2013-09-057-20/+27
* Add AArch32 DCPS{1,2,3} and HLT instructions.Richard Barton2013-09-054-7/+47
* Reverting 190043 for now.Tilmann Scheller2013-09-053-23/+3
* ARM: Add GPR register class excluding LR for use with the ADR instruction.Tilmann Scheller2013-09-053-3/+23
* ARM: Teach A15 SDOptimizer to properly handle D-reg by-lane.Jim Grosbach2013-09-041-0/+7
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