| Commit message (Expand) | Author | Age | Files | Lines |
|---|
| * | Alpha Scheduling classes | Andrew Lenharth | 2006-03-09 | 1 | -33/+44 |
| * | Add immediate forms of cmov and remove some cruft | Andrew Lenharth | 2006-02-01 | 1 | -3/+5 |
| * | minor renaming | Andrew Lenharth | 2006-01-26 | 1 | -1/+1 |
| * | allow R28 to be used for frame calculations without entirely removing it from... | Andrew Lenharth | 2006-01-26 | 1 | -18/+1 |
| * | stack and rpcc | Andrew Lenharth | 2006-01-16 | 1 | -3/+2 |
| * | Move brcond over and fix some imm patterns. This may be the last change befo... | Andrew Lenharth | 2006-01-01 | 1 | -2/+15 |
| * | add br pattern, unify JSR and BSR ISel instrs, and add BSR support for DAG | Andrew Lenharth | 2005-12-25 | 1 | -3/+6 |
| * | Unify the patterns for loads and stores. Now offset addressing should be | Andrew Lenharth | 2005-12-24 | 1 | -22/+3 |
| * | move loads and stores over. Smart addr selection comming | Andrew Lenharth | 2005-12-24 | 1 | -0/+12 |
| * | OK, this does wonders for broken stuff | Andrew Lenharth | 2005-12-06 | 1 | -0/+1 |
| * | added instructions with inverted immediates | Andrew Lenharth | 2005-12-06 | 1 | -17/+1 |
| * | These never trigger, but whatever | Andrew Lenharth | 2005-12-05 | 1 | -0/+18 |
| * | All sorts of stuff. | Andrew Lenharth | 2005-11-30 | 1 | -0/+10 |
| * | massive DAGISel patch. lots and lots more stuff compiles now | Andrew Lenharth | 2005-11-22 | 1 | -1/+3 |
| * | continued readcyclecounter support | Andrew Lenharth | 2005-11-11 | 1 | -0/+9 |
| * | whatever. Intermediate patch to see what breaks. Seems ok. | Andrew Lenharth | 2005-11-09 | 1 | -21/+11 |
| * | Simplify instinfo, set random bits on more fp insts, and fix 1 opcode | Andrew Lenharth | 2005-10-26 | 1 | -2/+3 |
| * | Well, the Constant matching pattern works. Can't say much about calls or glo... | Andrew Lenharth | 2005-10-22 | 1 | -1/+9 |
| * | Inst cleanup. As a bonus, operands are in the correct order for cmovs. Expe... | Andrew Lenharth | 2005-10-20 | 1 | -9/+11 |
| * | added a few 1 operand form stuff. Seems to break regalloc on alpha. sigh | Andrew Lenharth | 2005-10-20 | 1 | -0/+16 |
| * | ret 0; works, not much else | Andrew Lenharth | 2005-10-20 | 1 | -6/+10 |
| * | support bsr, and more .td simplification | Andrew Lenharth | 2005-07-28 | 1 | -1/+15 |
| * | simpilfy instruction encoding (and make the lines way shorter, aka Misha happ... | Andrew Lenharth | 2005-07-22 | 1 | -6/+76 |
| * | Make the rest of file header comments consistent in format and style | Misha Brukman | 2005-02-05 | 1 | -1/+1 |
| * | initial fp support | Andrew Lenharth | 2005-01-26 | 1 | -2/+2 |
| * | Clean ups, and taught the instruction selector about immediate forms | Andrew Lenharth | 2005-01-24 | 1 | -3/+2 |
| * | Let me introduce you to the early stages of the llvm backend for the alpha pr... | Andrew Lenharth | 2005-01-22 | 1 | -0/+109 |
