| Commit message (Expand) | Author | Age | Files | Lines |
|---|
| * | Access the TargetLoweringInfo from the TargetMachine object instead of cachin... | Bill Wendling | 2013-06-19 | 1 | -10/+10 |
| * | Don't cache the instruction and register info from the TargetMachine, because | Bill Wendling | 2013-06-07 | 1 | -3/+13 |
| * | Cache the TargetLowering info object as a pointer. | Bill Wendling | 2013-06-06 | 1 | -2/+2 |
| * | Track IR ordering of SelectionDAG nodes 2/4. | Andrew Trick | 2013-05-25 | 1 | -24/+24 |
| * | Make references to HexagonTargetMachine "const". | Krzysztof Parzyszek | 2013-05-06 | 1 | -3/+3 |
| * | Hexagon: Remove assembler mapped instruction definitions. | Jyotsna Verma | 2013-04-23 | 1 | -0/+11 |
| * | ArrayRefize getMachineNode(). No functionality change. | Michael Liao | 2013-04-19 | 1 | -6/+4 |
| * | Hexagon: Add and enable memops setbit, clrbit, &,|,+,- for byte, short, and w... | Jyotsna Verma | 2013-03-22 | 1 | -0/+40 |
| * | Hexagon: Use absolute addressing mode loads/stores for global+offset | Jyotsna Verma | 2013-02-13 | 1 | -8/+103 |
| * | Hexagon: Use TFR_cond with cmpb.[eq,gt,gtu] to handle | Jyotsna Verma | 2013-02-05 | 1 | -1/+8 |
| * | Use multiclass for post-increment store instructions. | Jyotsna Verma | 2013-01-29 | 1 | -2/+2 |
| * | Move all of the header files which are involved in modelling the LLVM IR | Chandler Carruth | 2013-01-02 | 1 | -1/+1 |
| * | Use the new script to sort the includes of every file under lib. | Chandler Carruth | 2012-12-03 | 1 | -1/+2 |
| * | Define signed const-ext immediate operands and their predicates. | Jyotsna Verma | 2012-11-28 | 1 | -0/+11 |
| * | Revert 156634 upon request until code improvement changes are made. | Brendon Cahoon | 2012-05-14 | 1 | -25/+6 |
| * | Hexagon constant extender support. | Brendon Cahoon | 2012-05-11 | 1 | -6/+25 |
| * | Hexagon V5 FP Support. | Sirish Pande | 2012-05-10 | 1 | -0/+24 |
| * | Add an MF argument to TRI::getPointerRegClass() and TII::getRegClass(). | Jakob Stoklund Olesen | 2012-05-07 | 1 | -1/+1 |
| * | Support for target dependent Hexagon VLIW packetizer. | Sirish Pande | 2012-05-03 | 1 | -8/+8 |
| * | Extensions of Hexagon V4 instructions. | Sirish Pande | 2012-05-03 | 1 | -3/+3 |
| * | Revert r155365, r155366, and r155367. All three of these have regression | Chandler Carruth | 2012-04-23 | 1 | -33/+5 |
| * | Hexagon V5 (floating point) support. | Sirish Pande | 2012-04-23 | 1 | -5/+33 |
| * | Convert more uses of XXXRegisterClass to &XXXRegClass. No functional change s... | Craig Topper | 2012-04-20 | 1 | -3/+3 |
| * | This reverts a long string of commits to the Hexagon backend. These | Chandler Carruth | 2012-04-18 | 1 | -33/+5 |
| * | Hexagon V5 (Floating Point) Support. | Sirish Pande | 2012-04-16 | 1 | -5/+33 |
| * | Emacs-tag and some comment fix for all ARM, CellSPU, Hexagon, MBlaze, MSP430,... | Jia Liu | 2012-02-18 | 1 | -1/+1 |
| * | Optimize redundant sign extends and negation of predicates. | Sirish Pande | 2012-02-15 | 1 | -2/+2 |
| * | Revert "Optimize redundant sign extends and negation of predicates" | Eric Christopher | 2012-02-15 | 1 | -2/+2 |
| * | Optimize redundant sign extends and negation of predicates | Sirish Pande | 2012-02-15 | 1 | -2/+2 |
| * | Convert assert(0) to llvm_unreachable | Craig Topper | 2012-02-07 | 1 | -2/+2 |
| * | More dead code removal (using -Wunreachable-code) | David Blaikie | 2012-01-20 | 1 | -2/+0 |
| * | Hexagon: Remove unused variables. | Benjamin Kramer | 2011-12-18 | 1 | -8/+0 |
| * | Hexagon backend support | Tony Linthicum | 2011-12-12 | 1 | -0/+1495 |
