| Commit message (Expand) | Author | Age | Files | Lines |
|---|
| * | Hexagon: Set isPredicatedNew flag on predicate new instructions. | Jyotsna Verma | 2013-04-12 | 2 | -22/+21 |
| * | Hexagon: Set isPredicatedFlase flag for all the instructions with negated pre... | Jyotsna Verma | 2013-04-12 | 2 | -21/+21 |
| * | Hexagon: Expand br_cc. | Jyotsna Verma | 2013-04-04 | 1 | -0/+2 |
| * | Remove unused typedef. | Duncan Sands | 2013-04-01 | 1 | -1/+0 |
| * | There is no longer any need to silence this compiler warning as the warning has | Duncan Sands | 2013-03-31 | 1 | -1/+1 |
| * | Hexagon: Add emitFrameIndexDebugValue function to emit debug information. | Jyotsna Verma | 2013-03-29 | 2 | -0/+14 |
| * | Hexagon: Disable DwarfUsesInlineInfoSection flag. | Jyotsna Verma | 2013-03-29 | 1 | -1/+0 |
| * | Hexagon: Replace switch-case in isDotNewInst with TSFlags. | Jyotsna Verma | 2013-03-28 | 4 | -176/+26 |
| * | Hexagon: Enable SupportDebugInfomation and DwarfInSection flags. | Jyotsna Verma | 2013-03-28 | 1 | -0/+2 |
| * | Hexagon: Use multiclass for gp-relative instructions. | Jyotsna Verma | 2013-03-28 | 2 | -1094/+204 |
| * | Switch to LLVM support function abs64 to keep VS2008 happy. | Tim Northover | 2013-03-27 | 1 | -1/+1 |
| * | Hexagon: Disable optimizations at O0. | Jyotsna Verma | 2013-03-27 | 1 | -18/+31 |
| * | Hexagon: Use multiclass for aslh, asrh, sxtb, sxth, zxtb and zxth. | Jyotsna Verma | 2013-03-26 | 2 | -186/+48 |
| * | Hexagon: Remove HexagonMCInst.h file. It has been replaced with MCTargetDesc/... | Jyotsna Verma | 2013-03-26 | 1 | -41/+0 |
| * | Hexagon: Add and enable memops setbit, clrbit, &,|,+,- for byte, short, and w... | Jyotsna Verma | 2013-03-22 | 5 | -494/+483 |
| * | Hexagon: Removed asserts regarding alignment and offset. | Jyotsna Verma | 2013-03-14 | 1 | -5/+4 |
| * | Cleanup #includes. | Jakub Staszak | 2013-03-10 | 1 | -1/+2 |
| * | DAGCombiner: Use correct value type for checking legality of BR_CC v3 | Tom Stellard | 2013-03-08 | 1 | -1/+3 |
| * | Hexagon: Add patterns for zero extended loads from i1->i64. | Jyotsna Verma | 2013-03-08 | 2 | -0/+24 |
| * | Hexagon: Handle i8, i16 and i1 Var Args. | Jyotsna Verma | 2013-03-07 | 1 | -0/+10 |
| * | Hexagon: Add support to lower block address. | Jyotsna Verma | 2013-03-07 | 4 | -0/+28 |
| * | reverting patch 176508. | Jyotsna Verma | 2013-03-05 | 4 | -28/+0 |
| * | Hexagon: Add support for lowering block address. | Jyotsna Verma | 2013-03-05 | 4 | -0/+28 |
| * | Hexagon: Expand addc, adde, subc and sube. | Jyotsna Verma | 2013-03-05 | 1 | -0/+23 |
| * | Hexagon: Use MO operand flags to mark constant extended instructions. | Jyotsna Verma | 2013-03-05 | 3 | -471/+43 |
| * | Hexagon: Add encoding bits to the TFR64 instructions. | Jyotsna Verma | 2013-03-05 | 1 | -20/+46 |
| * | Added FIXME for future Hexagon cleanup. | Andrew Trick | 2013-03-02 | 1 | -0/+3 |
| * | Hexagon: Add constant extender support framework. | Jyotsna Verma | 2013-03-01 | 4 | -23/+228 |
| * | Remove code copied from GenRegisterInfo.inc. | Andrew Trick | 2013-02-22 | 2 | -57/+0 |
| * | Move the eliminateCallFramePseudoInstr method from TargetRegisterInfo | Eli Bendersky | 2013-02-21 | 4 | -19/+20 |
| * | Hexagon: Expand cttz, ctlz, and ctpop for now. | Anshuman Dasgupta | 2013-02-21 | 1 | -0/+5 |
| * | Update TargetLowering ivars for name policy. | Jim Grosbach | 2013-02-20 | 1 | -2/+2 |
| * | Hexagon: Move HexagonMCInst.h to MCTargetDesc/HexagonMCInst.h. | Jyotsna Verma | 2013-02-20 | 10 | -32/+336 |
| * | Hexagon: Sync TSFlags in MCTargetDesc/HexagonBaseInfo.h with | Jyotsna Verma | 2013-02-19 | 1 | -28/+60 |
| * | Hexagon: Set appropriate TSFlags to the loads/stores with global address to | Jyotsna Verma | 2013-02-15 | 1 | -33/+25 |
| * | Hexagon: Change insn class to support instruction encoding. | Jyotsna Verma | 2013-02-14 | 5 | -259/+252 |
| * | Hexagon: Use multiclass for absolute addressing mode loads. | Jyotsna Verma | 2013-02-14 | 1 | -74/+35 |
| * | Hexagon: add support for predicate-GPR copies. | Anshuman Dasgupta | 2013-02-13 | 1 | -0/+12 |
| * | Hexagon: Use absolute addressing mode loads/stores for global+offset | Jyotsna Verma | 2013-02-13 | 6 | -1052/+224 |
| * | MIsched: HazardRecognizers are created for each DAG. Free them. | Andrew Trick | 2013-02-13 | 1 | -1/+3 |
| * | Hexagon: Add support to generate predicated absolute addressing mode | Jyotsna Verma | 2013-02-12 | 1 | -20/+123 |
| * | Extend Hexagon hardware loop generation to handle various additional cases: | Krzysztof Parzyszek | 2013-02-11 | 4 | -382/+1470 |
| * | Implement HexagonInstrInfo::analyzeCompare. | Krzysztof Parzyszek | 2013-02-11 | 2 | -0/+86 |
| * | Hexagon: Use TFR_cond with cmpb.[eq,gt,gtu] to handle | Jyotsna Verma | 2013-02-05 | 2 | -1/+214 |
| * | Hexagon: Use multiclass for absolute addressing mode stores. | Jyotsna Verma | 2013-02-05 | 1 | -102/+70 |
| * | Move MRI liveouts to Hexagon return instructions. | Jakob Stoklund Olesen | 2013-02-05 | 2 | -11/+10 |
| * | Hexagon: Add V4 compare instructions. Enable relationship mapping | Jyotsna Verma | 2013-02-05 | 1 | -16/+143 |
| * | Hexagon: Add V4 combine instructions and some more Def Pats for V2. | Jyotsna Verma | 2013-02-04 | 3 | -8/+135 |
| * | Replace LDriu*[bhdw]_indexed_V4 instructions with "def Pats". | Jyotsna Verma | 2013-02-01 | 3 | -504/+33 |
| * | Add appropriate TSFlags to the instructions that must be always extended. | Jyotsna Verma | 2013-02-01 | 1 | -148/+147 |
