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* Update aosp/master LLVM for rebase to r230699.Stephen Hines2015-03-231-96/+522
| | | | Change-Id: I2b5be30509658cb8266be782de0ab24f9099f9b9
* Update aosp/master LLVM for rebase to r222494.Stephen Hines2014-12-022-120/+190
| | | | Change-Id: Ic787f5e0124df789bd26f3f24680f45e678eef2d
* Update LLVM for rebase to r212749.Stephen Hines2014-07-211-13/+159
| | | | | | | Includes a cherry-pick of: r212948 - fixes a small issue with atomic calls Change-Id: Ib97bd980b59f18142a69506400911a6009d9df18
* Update LLVM for 3.5 rebase (r209712).Stephen Hines2014-05-292-39/+333
| | | | Change-Id: I149556c940fb7dc92d075273c87ff584f400941f
* Update to LLVM 3.5a.Stephen Hines2014-04-243-14/+87
| | | | Change-Id: Ifadecab779f128e62e430c2b4f6ddd84953ed617
* am b7485134: am 449fc261: Merge "llvm: convert makefiles to support multilib ↵Colin Cross2014-02-181-2/+0
|\ | | | | | | | | | | | | build" * commit 'b7485134a2cbecc47904988b4cfde24019ac4fa1': llvm: convert makefiles to support multilib build
| * llvm: convert makefiles to support multilib buildColin Cross2014-02-061-2/+0
| | | | | | | | | | | | | | | | Convert makefiles to allow for building two architectures at the same time. This will also cause make checkbuild to build the target libraries for all supported architectures. Change-Id: Ia5e6fe5b1186a67753faafd3532ed4cb280a8b10
* | Merge remote-tracking branch 'upstream/release_34' into merge-20140211Stephen Hines2014-02-111-44/+303
|\ \ | |/ |/| | | | | | | | | | | Conflicts: lib/Linker/LinkModules.cpp lib/Support/Unix/Signals.inc Change-Id: Ia54f291fa5dc828052d2412736e8495c1282aa64
| * [mips][msa] Fix immediate value of LSA instruction as it was being wrongly ↵Matheus Almeida2013-11-181-0/+16
| | | | | | | | | | | | | | | | | | | | | | encoded. The immediate field should be encoded as "imm - 1" as the CPU always adds one to that field. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@195004 91177308-0d34-0410-b5e6-96231b3b80d8
| * Support for microMIPS branch instructions.Zoran Jovanovic2013-11-041-0/+17
| | | | | | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@193992 91177308-0d34-0410-b5e6-96231b3b80d8
| * Support for microMIPS jump instructionsZoran Jovanovic2013-10-291-0/+15
| | | | | | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@193623 91177308-0d34-0410-b5e6-96231b3b80d8
| * [mips][msa] Direct Object Emission support for LD/ST instructions.Matheus Almeida2013-10-211-0/+19
| | | | | | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@193082 91177308-0d34-0410-b5e6-96231b3b80d8
| * [mips][msa] Direct Object Emission support for CTCMSA and CFCMSA. Matheus Almeida2013-10-211-0/+17
| | | | | | | | | | | | | | | | | | | | These instructions are logically related as they allow read/write of MSA control registers. Currently MSA control registers are emitted by number but hopefully that will change as soon as GAS starts accepting them by name as that would make the assembly easier to read. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@193078 91177308-0d34-0410-b5e6-96231b3b80d8
| * [mips][msa] Direct Object Emission for 3R instructions.Jack Carter2013-09-261-0/+17
| | | | | | | | | | | | | | | | | | This is the first set of instructions with a ".b" modifier thus we need to add the required code to disassemble a MSA128B register class. Patch by Matheus Almeida git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191415 91177308-0d34-0410-b5e6-96231b3b80d8
| * [mips][msa] Direct Object Emission support for the MSA instruction set. Jack Carter2013-09-251-0/+51
| | | | | | | | | | | | | | | | | | | | | | In more detail, this patch adds the ability to parse, encode and decode MSA registers ($w0-$w31). The format of 2RF instructions (MipsMSAInstrFormat.td) was updated so that we could attach a test case to this patch i.e., the test case parses, encodes and decodes 2 MSA instructions. Following patches will add the remainder of the instructions. Note that DecodeMSA128BRegisterClass is missing from MipsDisassembler.td because it's not yet required at this stage and having it would cause a compiler warning (unused function). Patch by Matheus Almeida git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191412 91177308-0d34-0410-b5e6-96231b3b80d8
| * This patch adds support for microMIPS disassembler and disassembler make ↵Vladimir Medic2013-09-061-8/+79
| | | | | | | | | | | | check tests. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@190144 91177308-0d34-0410-b5e6-96231b3b80d8
| * [mips] Use ptr_rc to simplify definitions of base+index load/store instructions.Akira Hatanaka2013-08-281-1/+20
| | | | | | | | | | | | | | | | Also, fix predicates. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@189432 91177308-0d34-0410-b5e6-96231b3b80d8
| * [mips] Define register class FGRH32 for the high half of the 64-bit floatingAkira Hatanaka2013-08-201-0/+17
| | | | | | | | | | | | | | | | | | | | point registers. We will need this register class later when we add definitions for instructions mfhc1 and mthc1. Also, remove sub-register indices sub_fpeven and sub_fpodd and use sub_lo and sub_hi instead. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@188842 91177308-0d34-0410-b5e6-96231b3b80d8
| * [mips] Rename DSPRegs.Akira Hatanaka2013-08-141-8/+8
| | | | | | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@188342 91177308-0d34-0410-b5e6-96231b3b80d8
| * [mips] Rename HIRegs and LORegs.Akira Hatanaka2013-08-141-18/+18
| | | | | | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@188341 91177308-0d34-0410-b5e6-96231b3b80d8
| * [mips] Rename accumulator register classes and FP register operands.Akira Hatanaka2013-08-081-9/+9
| | | | | | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@188020 91177308-0d34-0410-b5e6-96231b3b80d8
* | Merge commit '10251753b6897adcd22cc981c0cc42f348c109de' into merge-20130807Stephen Hines2013-08-071-71/+44
|\ \ | |/ | | | | | | | | | | | | Conflicts: lib/Archive/ArchiveReader.cpp lib/Support/Unix/PathV2.inc Change-Id: I29d8c1e321a4a380b6013f00bac6a8e4b593cc4e
| * Remove unused functions introduced in r172685 to unbreak the Clang -Werror buildDavid Blaikie2013-08-071-16/+0
| | | | | | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187838 91177308-0d34-0410-b5e6-96231b3b80d8
| * [mips] Rename register classes CPURegs and CPU64Regs.Akira Hatanaka2013-08-061-22/+22
| | | | | | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187832 91177308-0d34-0410-b5e6-96231b3b80d8
| * Stop leaking register infos in the disassemblers.Benjamin Kramer2013-08-031-2/+2
| | | | | | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187695 91177308-0d34-0410-b5e6-96231b3b80d8
| * [mips] Fix FP branch instructions to have explicit FP condition code registerAkira Hatanaka2013-07-261-16/+16
| | | | | | | | | | | | | | | | operands. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187238 91177308-0d34-0410-b5e6-96231b3b80d8
| * Fixing a buildbot failure:unused function.Vladimir Medic2013-07-161-14/+0
| | | | | | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@186403 91177308-0d34-0410-b5e6-96231b3b80d8
| * [Mips Disassembler] Have the DecodeCCRRegisterClass function use the getRegChad Rosier2013-06-261-1/+4
| | | | | | | | | | | | | | | | function to lookup the proper tablegen'ed register enumeration. Previously, it was using the encoded value directly. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185026 91177308-0d34-0410-b5e6-96231b3b80d8
* | Merge commit '100fbdd06be7590b23c4707a98cd605bdb519498' into merge_20130612Stephen Hines2013-06-121-1/+1
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| * Remove the Copied parameter from MemoryObject::readBytes.Benjamin Kramer2013-05-241-1/+1
| | | | | | | | | | | | | | | | | | | | There was exactly one caller using this API right, the others were relying on specific behavior of the default implementation. Since it's too hard to use it right just remove it and standardize on the default behavior. Defines away PR16132. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182636 91177308-0d34-0410-b5e6-96231b3b80d8
* | Merge remote-tracking branch 'upstream/master' into merge-20130502Stephen Hines2013-05-021-9/+43
|\ \ | |/ | | | | | | | | | | | | Conflicts: lib/Support/Unix/Signals.inc unittests/Transforms/Utils/Cloning.cpp Change-Id: I027581a4390ec3ce4cd8d33da8b5f4c0c7d372c8
| * [mips] DSP-ASE move from HI/LO register instructions.Akira Hatanaka2013-04-181-0/+34
| | | | | | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179739 91177308-0d34-0410-b5e6-96231b3b80d8
| * [mips] Fix DSP instructions to have explicit accumulator register operands.Akira Hatanaka2013-03-301-9/+9
| | | | | | | | | | | | | | | | Check that instruction selection can select multiply-add/sub DSP instructions from a pattern that doesn't have intrinsics. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178406 91177308-0d34-0410-b5e6-96231b3b80d8
* | Merge commit 'b3201c5cf1e183d840f7c99ff779d57f1549d8e5' into merge_20130226Stephen Hines2013-03-053-2/+16
|\ \ | |/ | | | | | | | | | | | | Conflicts: include/llvm/Support/ELF.h lib/Support/DeltaAlgorithm.cpp Change-Id: I24a4fbce62eb39d924efee3c687b55e1e17b30cd
| * Remove the form field from Mips16 instruction formats and set thingsReed Kotler2013-02-141-0/+14
| | | | | | | | | | | | | | | | | | | | up so that we can apply the direct object emitter patch. This patch should be a nop right now and it's test is to not break what is already there. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175126 91177308-0d34-0410-b5e6-96231b3b80d8
| * This is a resubmittal. For some reason it broke the bots yesterdayJack Carter2013-01-192-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | but I cannot reproduce the problem and have scrubed my sources and even tested with llvm-lit -v --vg. Formatting fixes. Mostly long lines and blank spaces at end of lines. Contributer: Jack Carter git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@172882 91177308-0d34-0410-b5e6-96231b3b80d8
| * This is a resubmittal. For some reason it broke the bots yesterdayJack Carter2013-01-171-0/+16
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | but I cannot reproduce the problem and have scrubed my sources and even tested with llvm-lit -v --vg. The Mips RDHWR (Read Hardware Register) instruction was not tested for assembler or dissassembler consumption. This patch adds that functionality. Contributer: Vladimir Medic git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@172685 91177308-0d34-0410-b5e6-96231b3b80d8
| * reverting 172579Jack Carter2013-01-161-16/+0
| | | | | | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@172594 91177308-0d34-0410-b5e6-96231b3b80d8
| * Akira,Jack Carter2013-01-161-0/+16
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Hope you are feeling better. The Mips RDHWR (Read Hardware Register) instruction was not tested for assembler or dissassembler consumption. This patch adds that functionality. Contributer: Vladimir Medic git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@172579 91177308-0d34-0410-b5e6-96231b3b80d8
| * MipsDisassembler.cpp: Prune DecodeHWRegs64RegisterClass() to suppress a ↵NAKAMURA Takumi2013-01-121-16/+0
| | | | | | | | | | | | warning. [-Wunused-function] git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@172319 91177308-0d34-0410-b5e6-96231b3b80d8
* | Update LLVM for merge to r171905.Stephen Hines2013-01-211-1/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Android.mk lib/Analysis/Android.mk lib/CodeGen/Android.mk lib/CodeGen/MachineScheduler.cpp - specify std::pop_heap() lib/IR/Android.mk - new from lib/VMCore lib/MC/Android.mk lib/MC/MCAssembler.cpp - put back pointer param (from reference). lib/Support/DeltaAlgorithm.cpp - iterator -> const_iterator ! lib/TableGen/Android.mk lib/Target/ARM/ARMJITInfo.cpp - Removed unused legacy JIT changes lib/Target/ARM/Android.mk lib/Target/ARM/AsmParser/Android.mk lib/Target/ARM/Disassembler/Android.mk lib/Target/ARM/MCTargetDesc/Android.mk lib/Target/Android.mk lib/Target/Mips/Android.mk lib/Target/Mips/Disassembler/Android.mk lib/Target/Mips/MCTargetDesc/Android.mk lib/Target/X86/Android.mk lib/Target/X86/AsmParser/Android.mk lib/Target/X86/Disassembler/Android.mk lib/Transforms/IPO/Android.mk lib/Transforms/Instrumentation/Android.mk lib/Transforms/Scalar/Android.mk lib/Transforms/Utils/Android.mk lib/Transforms/Vectorize/Android.mk lib/VMCore/Android.mk - moved to lib/IR llvm-gen-intrinsics.mk - new Intrinsics.td location utils/TableGen/Android.mk Change-Id: Ifebdb1716c372fd917a844c44be9d10df66434b0
* | Merge remote-tracking branch 'upstream/master' into merge-llvmStephen Hines2013-01-211-14/+33
|\ \ | |/ | | | | | | | | | | | | | | | | | | | | Conflicts: lib/CodeGen/AsmPrinter/AsmPrinter.cpp lib/CodeGen/AsmPrinter/AsmPrinterInlineAsm.cpp lib/MC/MCAssembler.cpp lib/Support/Atomic.cpp lib/Support/Memory.cpp lib/Target/ARM/ARMJITInfo.cpp Change-Id: Ib339baf88df5b04870c8df1bedcfe1f877ccab8d
| * Remove edis - the enhanced disassembler. Fixes PR14654.Roman Divacky2012-12-191-11/+0
| | | | | | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@170578 91177308-0d34-0410-b5e6-96231b3b80d8
| * Use the new script to sort the includes of every file under lib.Chandler Carruth2012-12-031-4/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Sooooo many of these had incorrect or strange main module includes. I have manually inspected all of these, and fixed the main module include to be the nearest plausible thing I could find. If you own or care about any of these source files, I encourage you to take some time and check that these edits were sensible. I can't have broken anything (I strictly added headers, and reordered them, never removed), but they may not be the headers you'd really like to identify as containing the API being implemented. Many forward declarations and missing includes were added to a header files to allow them to parse cleanly when included first. The main module rule does in fact have its merits. =] git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@169131 91177308-0d34-0410-b5e6-96231b3b80d8
| * MIPS DSP: add functions which decode DSP and accumulator registers.Akira Hatanaka2012-09-271-0/+29
| | | | | | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@164748 91177308-0d34-0410-b5e6-96231b3b80d8
* | Merge branch 'upstream' into merge_2Stephen Hines2012-08-231-8/+12
|\ \ | |/ | | | | | | | | | | Conflicts: lib/Target/ARM/ARMCodeEmitter.cpp Change-Id: I6702d340c733e9721499b5d85b13b96ad9c14eb5
| * Switch the fixed-length disassembler to be table-driven.Jim Grosbach2012-08-141-8/+12
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Refactor the TableGen'erated fixed length disassemblmer to use a table-driven state machine rather than a massive set of nested switch() statements. As a result, the ARM Disassembler (ARMDisassembler.cpp) builds much more quickly and generates a smaller end result. For a Release+Asserts build on a 16GB 3.4GHz i7 iMac w/ SSD: Time to compile at -O2 (averaged w/ hot caches): Previous: 35.5s New: 8.9s TEXT size: Previous: 447,251 New: 297,661 Builds in 25% of the time previously required and generates code 66% of the size. Execution time of the disassembler is only slightly slower (7% disassembling 10 million ARM instructions, 19.6s vs 21.0s). The new implementation has not yet been tuned, however, so the performance should almost certainly be recoverable should it become a concern. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@161888 91177308-0d34-0410-b5e6-96231b3b80d8
* | Fix mips disassembler makefile to build for mips, not arm.jeffhao2012-08-151-2/+1
| | | | | | | | Change-Id: I3a5491781ec580669f9af48f4d181571042fa4e7
* | Merge with LLVM upstream r160668 (Jul 24th 2012)Shih-wei Liao2012-08-031-113/+80
|\ \ | |/ | | | | | | | | | | | | | | | | Conflicts: include/llvm/Support/ELF.h lib/CodeGen/AsmPrinter/AsmPrinter.cpp lib/Support/Memory.cpp lib/Transforms/Instrumentation/AddressSanitizer.cpp Change-Id: Iddd658cf2eadc7165b2805b446d31af2c5c9917f
| * Reapply r158846.Akira Hatanaka2012-07-091-114/+77
| | | | | | | | | | | | | | | | Access mips register classes via MCRegisterInfo's functions instead of via the TargetRegisterClasses defined in MipsGenRegisterInfo.inc. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159953 91177308-0d34-0410-b5e6-96231b3b80d8
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