| Commit message (Expand) | Author | Age | Files | Lines |
|---|
| * | Add support for conditional branch instructions with 64-bit register operands. | Akira Hatanaka | 2011-10-11 | 1 | -11/+20 |
| * | Make changes necessary for supporting floating point load and store instructions | Akira Hatanaka | 2011-10-11 | 1 | -6/+18 |
| * | Simplify and update functions storeRegToStackSlot and loadRegFromStackSlot. | Akira Hatanaka | 2011-10-11 | 1 | -17/+23 |
| * | Simplify definition of FP move instructions. | Akira Hatanaka | 2011-10-08 | 1 | -1/+1 |
| * | Clean up MipsInstrInfo::copyPhysReg and handle copies from and to 64-bit integer | Akira Hatanaka | 2011-10-03 | 1 | -51/+44 |
| * | Revert r140731, "Define classes for unary and binary FP instructions and use ... | Jakob Stoklund Olesen | 2011-09-28 | 1 | -1/+1 |
| * | Define classes for unary and binary FP instructions and use them to define | Akira Hatanaka | 2011-09-28 | 1 | -1/+1 |
| * | Move TargetRegistry and TargetSelect from Target to Support where they belong. | Evan Cheng | 2011-08-24 | 1 | -1/+1 |
| * | Fix handling of double precision loads and stores when Mips1 is targeted. | Akira Hatanaka | 2011-08-16 | 1 | -26/+4 |
| * | Next round of MC refactoring. This patch factor MC table instantiations, MC | Evan Cheng | 2011-07-14 | 1 | -11/+0 |
| * | - Eliminate MCCodeEmitter's dependency on TargetMachine. It now uses MCInstrInfo | Evan Cheng | 2011-07-11 | 1 | -1/+12 |
| * | Lower MachineInstr to MC Inst and print to .s files. | Akira Hatanaka | 2011-07-07 | 1 | -0/+6 |
| * | Reverse order of operands of address operand mem so that the base operand comes | Akira Hatanaka | 2011-07-07 | 1 | -18/+18 |
| * | Hide the call to InitMCInstrInfo into tblgen generated ctor. | Evan Cheng | 2011-07-01 | 1 | -2/+2 |
| * | Improve Mips back-end's handling of DBG_VALUE. | Akira Hatanaka | 2011-07-01 | 1 | -0/+9 |
| * | Move CallFrameSetupOpcode and CallFrameDestroyOpcode to TargetInstrInfo. | Evan Cheng | 2011-06-28 | 1 | -1/+2 |
| * | Merge XXXGenRegisterNames.inc into XXXGenRegisterInfo.inc | Evan Cheng | 2011-06-28 | 1 | -0/+2 |
| * | - Rename TargetInstrDesc, TargetOperandInfo to MCInstrDesc and MCOperandInfo and | Evan Cheng | 2011-06-28 | 1 | -2/+2 |
| * | Reverse unnecessary changes made in r129606 and r129608. There is no change i... | Akira Hatanaka | 2011-04-15 | 1 | -10/+9 |
| * | Fix lines that have incorrect indentation or exceed 80 columns. There is no c... | Akira Hatanaka | 2011-04-15 | 1 | -9/+10 |
| * | Add code for analyzing FP branches. Clean up branch Analysis functions. | Akira Hatanaka | 2011-04-01 | 1 | -207/+128 |
| * | Added support for FP conditional move instructions and fixed bugs in handling... | Akira Hatanaka | 2011-03-31 | 1 | -5/+5 |
| * | Remove (hopefully) all trailing whitespaces from the mips backend. Patch by H... | Bruno Cardoso Lopes | 2011-03-04 | 1 | -37/+37 |
| * | Remove the isMoveInstr() hook. | Jakob Stoklund Olesen | 2010-07-16 | 1 | -47/+0 |
| * | RISC architectures get their memory operand folding for free. | Jakob Stoklund Olesen | 2010-07-11 | 1 | -74/+0 |
| * | Replace copyRegToReg with copyPhysReg for Mips. | Jakob Stoklund Olesen | 2010-07-11 | 1 | -50/+64 |
| * | Use COPY in targets | Jakob Stoklund Olesen | 2010-07-10 | 1 | -6/+2 |
| * | Add a DebugLoc parameter to TargetInstrInfo::InsertBranch(). This | Stuart Hastings | 2010-06-17 | 1 | -9/+8 |
| * | Add a DebugLoc argument to TargetInstrInfo::copyRegToReg, so that it | Dan Gohman | 2010-05-06 | 1 | -5/+4 |
| * | Add argument TargetRegisterInfo to loadRegFromStackSlot and storeRegToStackSlot. | Evan Cheng | 2010-05-06 | 1 | -2/+4 |
| * | No-ops emitted for scheduling don't correspond with anything in the | Dan Gohman | 2010-05-05 | 1 | -1/+0 |
| * | use DebugLoc default ctor instead of DebugLoc::getUnknownLoc() | Chris Lattner | 2010-04-02 | 1 | -5/+5 |
| * | Teach AnalyzeBranch, RemoveBranch and the branch | Dale Johannesen | 2010-04-02 | 1 | -1/+14 |
| * | load f64 +0.0 in a cleaner way. This fix part of PR5445 | Bruno Cardoso Lopes | 2010-01-19 | 1 | -9/+0 |
| * | Remove the target hook TargetInstrInfo::BlockHasNoFallThrough in favor of | Dan Gohman | 2009-12-05 | 1 | -16/+0 |
| * | Add proper emission of load/store double to stack slots for mips1 targets! | Bruno Cardoso Lopes | 2009-11-25 | 1 | -21/+43 |
| * | Support fp64 immediate zero, this fixes only part of PR5445 | Bruno Cardoso Lopes | 2009-11-13 | 1 | -3/+12 |
| * | Remove unused member functions. | Eli Friedman | 2009-07-24 | 1 | -45/+0 |
| * | llvm_unreachable->llvm_unreachable(0), LLVM_UNREACHABLE->llvm_unreachable. | Torok Edwin | 2009-07-14 | 1 | -2/+2 |
| * | assert(0) -> LLVM_UNREACHABLE. | Torok Edwin | 2009-07-11 | 1 | -2/+3 |
| * | Silence a warning when assertions are turned off. | Duncan Sands | 2009-07-03 | 1 | -0/+1 |
| * | Handle IMPLICIT_DEF with isUndef operand marker, part 2. This patch moves the... | Evan Cheng | 2009-07-01 | 1 | -4/+10 |
| * | Convert Alpha and Mips to use a MachineFunctionInfo subclass to | Dan Gohman | 2009-06-03 | 1 | -0/+29 |
| * | Added support for fround, fextend and FP_TO_SINT | Bruno Cardoso Lopes | 2009-05-27 | 1 | -10/+15 |
| * | Change MachineInstrBuilder::addReg() to take a flag instead of a list of | Bill Wendling | 2009-05-13 | 1 | -6/+6 |
| * | fix some warnings in release-asserts mode. | Chris Lattner | 2009-03-26 | 1 | -20/+19 |
| * | Removed AFGR32 register class | Bruno Cardoso Lopes | 2009-03-21 | 1 | -34/+18 |
| * | Factor out the code to add a MachineOperand to a MachineInstrBuilder. | Dan Gohman | 2009-02-18 | 1 | -18/+4 |
| * | Remove non-DebugLoc versions of BuildMI from IA64, Mips. | Dale Johannesen | 2009-02-13 | 1 | -6/+8 |
| * | Eliminate a couple of non-DebugLoc BuildMI variants. | Dale Johannesen | 2009-02-12 | 1 | -2/+4 |
