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* Fix a subtle difference between running clang vs llc for mips16.Reed Kotler2013-08-161-0/+3
* Reverted test commit (r188556)Daniel Sanders2013-08-161-1/+0
* Test commit. Just a blank lineDaniel Sanders2013-08-161-0/+1
* This patch implements wait instruction for mips. Examples are added in test f...Vladimir Medic2013-08-161-0/+11
* [Mips][msa] Added the simple builtins (madd_q to xori)Jack Carter2013-08-151-0/+842
* [Mips][msa] Added the simple builtins (fadd to ftq)Jack Carter2013-08-151-0/+467
* [Mips][msa] Added the simple builtins (add_a to dpsub[su], ilvev to ldi)Jack Carter2013-08-156-20/+1238
* [mips] Fix bug in parsing accumulator registers.Akira Hatanaka2013-08-141-2/+2
* [mips] Use register operands instead of register classes in DSP instructionAkira Hatanaka2013-08-143-209/+309
* [mips] Rename DSPRegs.Akira Hatanaka2013-08-145-113/+117
* [mips] Rename HIRegs and LORegs.Akira Hatanaka2013-08-1410-84/+83
* [mips] Properly parse registers that appear in inline-asm constraints.Akira Hatanaka2013-08-142-0/+86
* [Mips][msa] Added initial MSA support.Jack Carter2013-08-138-1/+176
* [Mips] Support for unaligned load/store microMips instructionsJack Carter2013-08-139-3/+131
* This patch introduces changes to MipsAsmParser register parsing routines. The...Vladimir Medic2013-08-131-176/+146
* This patch implements ei and di instructions for mips. Test cases are added.Vladimir Medic2013-08-122-1/+30
* Remove global construction. const char* is sufficient here.Benjamin Kramer2013-08-121-2/+2
* Don't generate floating point stubs for mips16 code if the functionReed Kotler2013-08-111-1/+13
* Incorrect JAL instruction attributes caused the optimizer to make a wrongReed Kotler2013-08-101-3/+0
* Add another intrinsic that LLVM gives an incorrect prototype to.Reed Kotler2013-08-091-0/+1
* Mips ELF: MicroMips direct object Little endian support. Jack Carter2013-08-081-4/+15
* [mips] Rename accumulator register classes and FP register operands.Akira Hatanaka2013-08-0812-246/+246
* [mips] Mark pseudo instructions as code-gen only.Akira Hatanaka2013-08-081-5/+5
* [mips] Delete register class HWRegs64.Akira Hatanaka2013-08-085-56/+3
* Create a pattern for the "trap" instruction.Reed Kotler2013-08-072-0/+29
* Remove unused functions introduced in r172685 to unbreak the Clang -Werror buildDavid Blaikie2013-08-071-16/+0
* [mips] Rename register classes CPURegs and CPU64Regs.Akira Hatanaka2013-08-0622-622/+622
* [mips] Mark instructions defined in Mips64InstrInfo.td that are duplicates ofAkira Hatanaka2013-08-063-54/+41
* [mips] Delete unnecessary InstAliases. Also, clear some of the InstAlias'Akira Hatanaka2013-08-063-38/+18
* [mips] Replace usages of register classes with register operands. Also, removeAkira Hatanaka2013-08-067-168/+221
* Target/*/CMakeLists.txt: Add the dependency to CommonTableGen explicitly for ...NAKAMURA Takumi2013-08-061-1/+1
* Add the saving of S2. This is needed for some of the floating pointReed Kotler2013-08-042-6/+10
* Clean up code for Mips16 large frame handling.Reed Kotler2013-08-046-35/+138
* Stop leaking register infos in the disassemblers.Benjamin Kramer2013-08-031-2/+2
* [mips] Expand vector truncating stores and extending loads.Akira Hatanaka2013-08-021-0/+14
* [mips] Make load/store accumulator pseudo instructions codeGenOnly. Also,Akira Hatanaka2013-08-012-22/+11
* Fix some issues with Mips16 floating when certain intrinsics are present.Reed Kotler2013-08-011-0/+52
* Moving definition of MnemonicContainsDot field from class Instruction to clas...Vladimir Medic2013-08-012-1/+1
* Fix some misc. issues with Mips16 fp stubs.Reed Kotler2013-08-011-2/+7
* Add an omitted IsCall=1.Reed Kotler2013-08-011-0/+1
* [mips] Rename instruction DANDi to ANDi64.Akira Hatanaka2013-07-311-4/+4
* [mips] Define instruction itineraries IIArith and IILogic.Akira Hatanaka2013-07-315-38/+49
* [mips] Delete instruction format for "bal".Akira Hatanaka2013-07-301-11/+0
* [mips] Define "bal" as a pseudo instruction. Also, fix bug in the InstAlias thatAkira Hatanaka2013-07-302-5/+9
* This patch implements parsing of mips FCC register operands. The example inst...Vladimir Medic2013-07-304-14/+66
* [mips] Add comment and simplify function.Akira Hatanaka2013-07-291-23/+14
* [mips] Implement llvm.trap intrinsic.Akira Hatanaka2013-07-262-0/+7
* [mips] Fix FP conditional move instructions to have explicit FP condition codeAkira Hatanaka2013-07-264-13/+14
* [mips] Fix FP branch instructions to have explicit FP condition code registerAkira Hatanaka2013-07-265-25/+41
* [mips] Increase the number of floating point condition code registers to eight.Akira Hatanaka2013-07-261-3/+5
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