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* Renaming ISD::BIT_CONVERT to ISD::BITCAST to better reflect the LLVM IR concept.Wesley Peck2010-11-231-141/+141
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119990 91177308-0d34-0410-b5e6-96231b3b80d8
* Move hasFP() and few related hooks to TargetFrameInfo.Anton Korobeynikov2010-11-185-28/+25
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119740 91177308-0d34-0410-b5e6-96231b3b80d8
* Attempt to unbreak cmake-based buildsAnton Korobeynikov2010-11-151-0/+1
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119098 91177308-0d34-0410-b5e6-96231b3b80d8
* First step of huge frame-related refactoring: move emit{Prologue,Epilogue} ↵Anton Korobeynikov2010-11-156-290/+366
| | | | | | out of TargetRegisterInfo to TargetFrameInfo, which is definitely much better suitable place git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119097 91177308-0d34-0410-b5e6-96231b3b80d8
* move all the target's asmprinters into the main target. The piece Chris Lattner2010-11-145-27/+2
| | | | | | | | | that should be split out is the InstPrinter (if a target is mc'ized). This change makes all the targets be consistent. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119056 91177308-0d34-0410-b5e6-96231b3b80d8
* Enable mips32 mul instruction. Patch by Akira Hatanaka <ahatanaka@mips.com>Bruno Cardoso Lopes2010-11-123-3/+6
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118864 91177308-0d34-0410-b5e6-96231b3b80d8
* Add clo instruction. Patch by Akira Hatanaka (ahatanaka@mips.com) with some ↵Bruno Cardoso Lopes2010-11-102-8/+12
| | | | | | minor tweaks git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118667 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix trailing whitespace and style, no functionality changeBruno Cardoso Lopes2010-11-091-170/+95
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118515 91177308-0d34-0410-b5e6-96231b3b80d8
* Initial support for Mips32 and Mips32r2. Patch contributed by Akira Hatanaka ↵Bruno Cardoso Lopes2010-11-083-12/+22
| | | | | | (ahatanaka@mips.com) git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118447 91177308-0d34-0410-b5e6-96231b3b80d8
* In the calling convention logic, ValVT is always a legal type,Duncan Sands2010-11-041-3/+3
| | | | | | | | and as such can be represented by an MVT - the more complicated EVT is not needed. Use MVT for ValVT everywhere. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118245 91177308-0d34-0410-b5e6-96231b3b80d8
* Inside the calling convention logic LocVT is always a simpleDuncan Sands2010-11-031-2/+2
| | | | | | | | | | | value type, so there is no point in passing it around using an EVT. Use the simpler MVT everywhere. Rather than trying to propagate this information maximally in all the code that using the calling convention stuff, I chose to do a mainly low impact change instead. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118167 91177308-0d34-0410-b5e6-96231b3b80d8
* Inline asm multiple alternative constraints development phase 2 - improved ↵John Thompson2010-10-292-0/+36
| | | | | | basic logic, added initial platform support. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117667 91177308-0d34-0410-b5e6-96231b3b80d8
* Add support to model pipeline bypass / forwarding.Evan Cheng2010-09-281-1/+1
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115005 91177308-0d34-0410-b5e6-96231b3b80d8
* Removed a bunch of unnecessary target_link_libraries.Oscar Fuentes2010-09-281-2/+0
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114999 91177308-0d34-0410-b5e6-96231b3b80d8
* Remove trailing spaces of MipsMachineFunction.hChe-Liang Chiou2010-09-281-17/+17
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114948 91177308-0d34-0410-b5e6-96231b3b80d8
* Remove trailing spaces of MipsTargetObjectFile.cppChe-Liang Chiou2010-09-281-10/+10
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114947 91177308-0d34-0410-b5e6-96231b3b80d8
* fix a long standing wart: all the ComplexPattern's were beingChris Lattner2010-09-211-6/+4
| | | | | | | | | | | | passed the root of the match, even though only a few patterns actually needed this (one in X86, several in ARM [which should be refactored anyway], and some in CellSPU that I don't feel like detangling). Instead of requiring all ComplexPatterns to take the dead root, have targets opt into getting the root by putting SDNPWantRoot on the ComplexPattern. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114471 91177308-0d34-0410-b5e6-96231b3b80d8
* eliminate some uses of the getStore overload.Chris Lattner2010-09-211-3/+6
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114453 91177308-0d34-0410-b5e6-96231b3b80d8
* convert the targets off the non-MachinePointerInfo of getLoad.Chris Lattner2010-09-211-6/+10
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114410 91177308-0d34-0410-b5e6-96231b3b80d8
* Remove Predicate_* calls from MipsJakob Stoklund Olesen2010-09-031-2/+3
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@112919 91177308-0d34-0410-b5e6-96231b3b80d8
* Simplify eliminateFrameIndex() interface back down now that PEI doesn't needJim Grosbach2010-08-262-7/+4
| | | | | | to try to re-use scavenged frame index reference registers. rdar://8277890 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@112241 91177308-0d34-0410-b5e6-96231b3b80d8
* Don't call Predicate_* in Mips.Jakob Stoklund Olesen2010-08-182-9/+4
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@111468 91177308-0d34-0410-b5e6-96231b3b80d8
* fix emacs language spec's, patch by Edmund Grimley-Evans!Chris Lattner2010-08-177-7/+7
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@111241 91177308-0d34-0410-b5e6-96231b3b80d8
* Reapply r110396, with fixes to appease the Linux buildbot gods.Owen Anderson2010-08-061-1/+1
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110460 91177308-0d34-0410-b5e6-96231b3b80d8
* Revert r110396 to fix buildbots.Owen Anderson2010-08-061-1/+1
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110410 91177308-0d34-0410-b5e6-96231b3b80d8
* Don't use PassInfo* as a type identifier for passes. Instead, use the ↵Owen Anderson2010-08-051-1/+1
| | | | | | | | | address of the static ID member as the sole unique type identifier. Clean up APIs related to this change. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110396 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix PR7174, a couple o Mips fixes:Bruno Cardoso Lopes2010-07-202-1/+21
| | | | | | | | | | | | | - Fix a typo for PIC check during jmp table lowering - Also fix the "first jump table basic block is not considered only reachable by fall through" problem, use this ad-hoc solution until I come up with something better. Patch by stetorvs@gmail.com git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108820 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix Mips PR7473. Patch by stetorvs@gmail.comBruno Cardoso Lopes2010-07-201-3/+3
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108816 91177308-0d34-0410-b5e6-96231b3b80d8
* Remove the isMoveInstr() hook.Jakob Stoklund Olesen2010-07-162-53/+0
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108567 91177308-0d34-0410-b5e6-96231b3b80d8
* Don't pass StringRef by reference.Benjamin Kramer2010-07-142-3/+3
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108366 91177308-0d34-0410-b5e6-96231b3b80d8
* RISC architectures get their memory operand folding for free.Jakob Stoklund Olesen2010-07-112-86/+0
| | | | | | | | The only folding these load/store architectures can do is converting COPY into a load or store, and the target independent part of foldMemoryOperand already knows how to do that. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108099 91177308-0d34-0410-b5e6-96231b3b80d8
* Replace copyRegToReg with copyPhysReg for Mips.Jakob Stoklund Olesen2010-07-112-56/+68
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108066 91177308-0d34-0410-b5e6-96231b3b80d8
* Use COPY in targetsJakob Stoklund Olesen2010-07-101-6/+2
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108063 91177308-0d34-0410-b5e6-96231b3b80d8
* Split the SDValue out of OutputArg so that SelectionDAG-independentDan Gohman2010-07-072-2/+6
| | | | | | | code can do calling-convention queries. This obviates OutputArgReg. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107786 91177308-0d34-0410-b5e6-96231b3b80d8
* Propagate debug loc.Devang Patel2010-07-061-4/+4
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107710 91177308-0d34-0410-b5e6-96231b3b80d8
* Reapply r107655 with fixes; insert the pseudo instruction intoDan Gohman2010-07-061-16/+15
| | | | | | | | the block before calling the expansion hook. And don't put EFLAGS in a mbb's live-in list twice. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107691 91177308-0d34-0410-b5e6-96231b3b80d8
* Revert r107655.Dan Gohman2010-07-061-15/+16
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107668 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix a bunch of custom-inserter functions to handle the case whereDan Gohman2010-07-061-16/+15
| | | | | | | the pseudo instruction is not at the end of the block. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107655 91177308-0d34-0410-b5e6-96231b3b80d8
* Remove isSS argument from CreateFixedObject. Fixed objects cannot be spill ↵Evan Cheng2010-07-031-5/+5
| | | | | | slots so it's always false. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107550 91177308-0d34-0410-b5e6-96231b3b80d8
* Remove isTwoAddress from Mips.Eric Christopher2010-06-211-1/+1
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106465 91177308-0d34-0410-b5e6-96231b3b80d8
* Add a DebugLoc parameter to TargetInstrInfo::InsertBranch(). ThisStuart Hastings2010-06-172-10/+10
| | | | | | | | | | | | | addresses a longstanding deficiency noted in many FIXMEs scattered across all the targets. This effectively moves the problem up one level, replacing eleven FIXMEs in the targets with eight FIXMEs in CodeGen, plus one path through FastISel where we actually supply a DebugLoc, fixing Radar 7421831. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106243 91177308-0d34-0410-b5e6-96231b3b80d8
* Remove the TargetRegisterClass member from CalleeSavedInfoRafael Espindola2010-06-022-5/+7
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@105344 91177308-0d34-0410-b5e6-96231b3b80d8
* cleanupRafael Espindola2010-06-022-31/+0
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@105322 91177308-0d34-0410-b5e6-96231b3b80d8
* Replace the SubRegSet tablegen class with a less error-prone mechanism.Jakob Stoklund Olesen2010-05-261-20/+6
| | | | | | | | | | | | | | | | A Register with subregisters must also provide SubRegIndices for adressing the subregisters. TableGen automatically inherits indices for sub-subregisters to minimize typing. CompositeIndices may be specified for the weirder cases such as the XMM sub_sd index that returns the same register, and ARM NEON Q registers where both D subregs have ssub_0 and ssub_1 sub-subregs. It is now required that all subregisters are named by an index, and a future patch will also require inherited subregisters to be named. This is necessary to allow composite subregister indices to be reduced to a single index. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104704 91177308-0d34-0410-b5e6-96231b3b80d8
* Revert "Replace the SubRegSet tablegen class with a less error-prone mechanism."Jakob Stoklund Olesen2010-05-261-6/+20
| | | | | | This reverts commit 104654. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104660 91177308-0d34-0410-b5e6-96231b3b80d8
* Replace the SubRegSet tablegen class with a less error-prone mechanism.Jakob Stoklund Olesen2010-05-261-20/+6
| | | | | | | | | | | | | | | | A Register with subregisters must also provide SubRegIndices for adressing the subregisters. TableGen automatically inherits indices for sub-subregisters to minimize typing. CompositeIndices may be specified for the weirder cases such as the XMM sub_sd index that returns the same register, and ARM NEON Q registers where both D subregs have ssub_0 and ssub_1 sub-subregs. It is now required that all subregisters are named by an index, and a future patch will also require inherited subregisters to be named. This is necessary to allow composite subregister indices to be reduced to a single index. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104654 91177308-0d34-0410-b5e6-96231b3b80d8
* Remove NumberHack entirely.Jakob Stoklund Olesen2010-05-251-2/+2
| | | | | | | SubRegIndex instances are now numbered uniquely the same way Register instances are - in lexicographical order by name. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104627 91177308-0d34-0410-b5e6-96231b3b80d8
* Switch SubRegSet to using symbolic SubRegIndicesJakob Stoklund Olesen2010-05-241-8/+8
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104571 91177308-0d34-0410-b5e6-96231b3b80d8
* Replace the tablegen RegisterClass field SubRegClassList with an alist-like dataJakob Stoklund Olesen2010-05-241-1/+1
| | | | | | | | | | | structure that represents a mapping without any dependencies on SubRegIndex numbering. This brings us closer to being able to remove the explicit SubRegIndex numbering, and it is now possible to specify any mapping without inventing *_INVALID register classes. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104563 91177308-0d34-0410-b5e6-96231b3b80d8
* SubRegIndex'ize MipsJakob Stoklund Olesen2010-05-243-17/+10
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104514 91177308-0d34-0410-b5e6-96231b3b80d8
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