aboutsummaryrefslogtreecommitdiffstats
path: root/lib/Target/PowerPC/PPCInstrInfo.cpp
Commit message (Collapse)AuthorAgeFilesLines
* convert PPC::BCC to use the 'pred' operand instead of separate predicateChris Lattner2006-11-171-3/+3
| | | | | | | | | value and CR reg #. This requires swapping the order of these everywhere that touches BCC and requires us to write custom matching logic for PPCcondbranch :( git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@31835 91177308-0d34-0410-b5e6-96231b3b80d8
* rename PPC::COND_BRANCH to PPC::BCCChris Lattner2006-11-171-7/+7
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@31834 91177308-0d34-0410-b5e6-96231b3b80d8
* start using PPC predicates more consistently.Chris Lattner2006-11-171-1/+2
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@31833 91177308-0d34-0410-b5e6-96231b3b80d8
* Properly transfer kill / dead info.Evan Cheng2006-11-151-0/+10
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@31765 91177308-0d34-0410-b5e6-96231b3b80d8
* Matches MachineInstr changes.Evan Cheng2006-11-131-1/+1
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@31712 91177308-0d34-0410-b5e6-96231b3b80d8
* implement the BlockHasNoFallThrough hookChris Lattner2006-10-281-0/+11
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@31264 91177308-0d34-0410-b5e6-96231b3b80d8
* Implement support for branch reversal, fix a bug in branch analysis.Chris Lattner2006-10-211-2/+5
| | | | | | | | | | | | | | | | | This provides stuff like: cmpw cr0, r15, r29 mr r14, r15 - bge cr0, LBB3_111 ;bb656 - b LBB3_90 ;bb501 + blt cr0, LBB3_90 ;bb501 LBB3_111: ;bb656 lwz r18, 68(r1) which is particularly good for dispatch group formation. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@31101 91177308-0d34-0410-b5e6-96231b3b80d8
* Simplify code, no functionality changeChris Lattner2006-10-211-4/+2
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@31097 91177308-0d34-0410-b5e6-96231b3b80d8
* implement support for inserting a cond branchChris Lattner2006-10-211-4/+8
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@31096 91177308-0d34-0410-b5e6-96231b3b80d8
* add support for inserting an uncond branchChris Lattner2006-10-171-2/+8
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@31003 91177308-0d34-0410-b5e6-96231b3b80d8
* implement branch inspection/modification methods.Chris Lattner2006-10-131-0/+93
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@30946 91177308-0d34-0410-b5e6-96231b3b80d8
* In 64-bit mode, 64-bit GPRs are callee saved, not 32-bit ones.Chris Lattner2006-07-111-1/+2
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@29096 91177308-0d34-0410-b5e6-96231b3b80d8
* Rename OR4 -> OR. Move some PPC64-specific stuff to the 64-bit fileChris Lattner2006-06-201-1/+1
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28889 91177308-0d34-0410-b5e6-96231b3b80d8
* Implement the getPointerRegClass method, which is required for the ptr_rcChris Lattner2006-06-171-3/+13
| | | | | | | magic to work. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28847 91177308-0d34-0410-b5e6-96231b3b80d8
* Move some methods out of MachineInstr into MachineOperandChris Lattner2006-05-041-2/+2
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28102 91177308-0d34-0410-b5e6-96231b3b80d8
* teach the ppc backend how to spill/reload vector regsChris Lattner2006-03-161-1/+1
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26806 91177308-0d34-0410-b5e6-96231b3b80d8
* Add support for copying registers. still needed: spilling and reloading themChris Lattner2006-03-161-1/+1
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26800 91177308-0d34-0410-b5e6-96231b3b80d8
* implement TII::insertNoopChris Lattner2006-03-051-0/+5
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26562 91177308-0d34-0410-b5e6-96231b3b80d8
* add 64b gpr store to the possible list of isStoreToStackSlot opcodes.Nate Begeman2006-02-021-1/+1
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@25916 91177308-0d34-0410-b5e6-96231b3b80d8
* implement isStoreToStackSlot for PPCChris Lattner2006-02-021-1/+18
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@25914 91177308-0d34-0410-b5e6-96231b3b80d8
* Move isLoadFrom/StoreToStackSlot from MRegisterInfo to TargetInstrInfo,a far ↵Chris Lattner2006-02-021-0/+19
| | | | | | more logical place. Other methods should also be moved if anyoneis interested. :) git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@25913 91177308-0d34-0410-b5e6-96231b3b80d8
* teach ppc backend these are copiesChris Lattner2005-10-191-1/+2
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23813 91177308-0d34-0410-b5e6-96231b3b80d8
* First bits of 64 bit PowerPC stuff, currently disabled. A lot of this isNate Begeman2005-10-181-1/+1
| | | | | | | purely mechanical. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23778 91177308-0d34-0410-b5e6-96231b3b80d8
* More PPC32 -> PPC changes, as well as merging some classes that wereNate Begeman2005-10-161-6/+6
| | | | | | | redundant after the change. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23759 91177308-0d34-0410-b5e6-96231b3b80d8
* Rename PPC32*.h to PPC*.hChris Lattner2005-10-141-1/+1
| | | | | | | This completes the grand PPC file renaming git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23745 91177308-0d34-0410-b5e6-96231b3b80d8
* Rename PowerPC*.h to PPC*.hChris Lattner2005-10-141-1/+1
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23743 91177308-0d34-0410-b5e6-96231b3b80d8
* Eliminate PowerPC.td and PPC32.td, consolidating them into PPC.tdChris Lattner2005-10-141-2/+2
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23738 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix a CQ regression from my patch to split F32/F64 into seperate registerChris Lattner2005-10-071-1/+2
| | | | | | | | classes on PPC. We were emitting fmr instructions to do fp extensions, which weren't getting coallesced. This fixes Regression/CodeGen/PowerPC/fpcopy.ll git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23654 91177308-0d34-0410-b5e6-96231b3b80d8
* Modify the ppc backend to use two register classes for FP: F8RC and F4RC.Chris Lattner2005-10-011-1/+1
| | | | | | | | These are used to represent float and double values, and the two regclasses contain the same physical registers. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23577 91177308-0d34-0410-b5e6-96231b3b80d8
* Teach the code generator that rlwimi is commutable if the rotate amountChris Lattner2005-09-091-0/+32
| | | | | | | | | is zero. This lets the register allocator elide some copies in some cases. This implements CodeGen/PowerPC/rlwimi-commute.ll git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23292 91177308-0d34-0410-b5e6-96231b3b80d8
* Remove trailing whitespaceMisha Brukman2005-04-211-2/+2
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@21425 91177308-0d34-0410-b5e6-96231b3b80d8
* Initial support for allocation condition registersNate Begeman2005-04-121-0/+8
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@21246 91177308-0d34-0410-b5e6-96231b3b80d8
* Add ori reg, reg, 0 as a move instruction. This can be generated fromNate Begeman2004-10-071-0/+11
| | | | | | | | | | | | | | | | | | loading a 32bit constant into a register whose low halfword is all zeroes. We now omit the ori after the lis for the following C code: int bar(int y) { return y * 0x00F0000; } _bar: .LBB_bar_0: ; entry ; IMPLICIT_DEF lis r2, 15 mullw r3, r3, r2 blr git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@16825 91177308-0d34-0410-b5e6-96231b3b80d8
* PowerPC 32-/64-bit split: Part I, PPC32* bit files, adapted from former PowerPC*Misha Brukman2004-08-171-0/+59
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@15850 91177308-0d34-0410-b5e6-96231b3b80d8
generated by cgit v1.1 at 2025-05-11 22:28:51 +0000