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path: root/lib/Target/PowerPC/PPCRegisterInfo.cpp
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* Move all of the header files which are involved in modelling the LLVM IRChandler Carruth2013-01-021-4/+4
* Remove the Function::getFnAttributes method in favor of using the AttributeSetBill Wendling2012-12-301-1/+2
* Rename the 'Attributes' class to 'Attribute'. It's going to represent a singl...Bill Wendling2012-12-191-1/+1
* Use the new script to sort the includes of every file under lib.Chandler Carruth2012-12-031-13/+13
* Using const cast to alleviate a warning.Joe Abbey2012-11-161-1/+2
* Revert the majority of the next patch in the address space series:Chandler Carruth2012-11-011-1/+1
* Resubmit the changes to llvm core to update the functions to support differen...Micah Villmow2012-10-151-1/+1
* Revert 165732 for further review.Micah Villmow2012-10-111-1/+1
* Add in the first iteration of support for llvm/clang/lldb to allow variable p...Micah Villmow2012-10-111-1/+1
* Create enums for the different attributes.Bill Wendling2012-10-091-1/+1
* Remove the `hasFnAttr' method from Function.Bill Wendling2012-09-261-1/+1
* Change unsigned to uint32_t to match base class declaration and other targets.Craig Topper2012-09-161-1/+1
* This patch corrects logic in PPCFrameLowering for save and restore of ...Roman Divacky2012-09-121-1/+31
* Mark most PPC register classes to avoid write-after-write.Hal Finkel2012-06-191-0/+14
* Add support for generating reg+reg preinc stores on PPC.Hal Finkel2012-06-191-6/+6
* Add an MF argument to TRI::getPointerRegClass() and TII::getRegClass().Jakob Stoklund Olesen2012-05-071-1/+2
* This patch fixes a problem which arose when using the Post-RA schedulerPreston Gurd2012-04-231-0/+6
* PPC::DBG_VALUE must use Reg+Imm frame-index elimination even for large offset...Hal Finkel2012-03-221-1/+2
* Reorder includes in Target backends to following coding standards. Remove som...Craig Topper2012-03-171-1/+1
* Convert PowerPC to register mask operands.Roman Divacky2012-03-061-94/+10
* Use uint16_t to store registers in callee saved register tables to reduce siz...Craig Topper2012-03-041-5/+5
* Emacs-tag and some comment fix for all ARM, CellSPU, Hexagon, MBlaze, MSP430,...Jia Liu2012-02-181-1/+1
* Cleanup PPC RLWINM8 vs RLWINMHal Finkel2012-01-161-1/+1
* Cleanup stack/frame register define/kill states. This fixes two bugs:Hal Finkel2011-12-301-9/+9
* Make CR spill and restore use a reserved register. These operations cannot us...Hal Finkel2011-12-101-10/+18
* make CR spill and restore 64-bit clean (no functional change), and fix some o...Hal Finkel2011-12-071-3/+3
* make base register selection used in eliminateFrameIndex 64-bit cleanHal Finkel2011-12-071-8/+13
* add RESTORE_CR and support CR unspillsHal Finkel2011-12-061-4/+45
* remove old FIXMEHal Finkel2011-12-061-1/+0
* enable PPC register scavenging by default (update tests and remove some FIXMEs)Hal Finkel2011-12-051-11/+7
* don't include CR bit subregs in callee-saved listHal Finkel2011-12-051-16/+0
* add register pressure for CR regsHal Finkel2011-12-051-0/+2
* Move global variables in TargetMachine into new TargetOptions class. As an APINick Lewycky2011-12-021-1/+2
* add basic PPC register-pressure feedback; adjust the vaarg test to match the ...Hal Finkel2011-11-221-0/+21
* Refactor PPC target to separate MC routines from Target routines.Evan Cheng2011-07-251-44/+1
* Move getInitialFrameState from TargetFrameInfo to MCAsmInfo (suggestions forEvan Cheng2011-07-181-1/+0
* Sink getDwarfRegNum, getLLVMRegNum, getSEHRegNum from TargetRegisterInfo downEvan Cheng2011-07-181-29/+4
* Next round of MC refactoring. This patch factor MC table instantiations, MCEvan Cheng2011-07-141-1/+0
* Move CallFrameSetupOpcode and CallFrameDestroyOpcode to TargetInstrInfo.Evan Cheng2011-06-281-2/+1
* Hide more details in tablegen generated MCRegisterInfo ctor function.Evan Cheng2011-06-281-2/+1
* Merge XXXGenRegisterDesc.inc XXXGenRegisterNames.inc XXXGenRegisterInfo.h.incEvan Cheng2011-06-271-1/+3
* Starting to refactor Target to separate out code that's needed to fully describeEvan Cheng2011-06-241-3/+4
* Fix a few places where 32bit instructions/registerset were used on PPC64.Roman Divacky2011-06-171-1/+2
* Use the dwarf->llvm mapping to print register names in the cfiRafael Espindola2011-05-301-0/+8
* Split ppc dwarf regnums into ppc64 and ppc32 flavours.Rafael Espindola2011-05-301-1/+12
* Rename TargetFrameInfo into TargetFrameLowering. Also, put couple of FIXMEs a...Anton Korobeynikov2011-01-101-7/+7
* Restore the behavior of frame lowering before my refactoring.Anton Korobeynikov2010-12-181-2/+3
* Move more PEI-related hooks to TFIAnton Korobeynikov2010-11-271-274/+8
* Move getInitialFrameState() to TargetFrameInfoAnton Korobeynikov2010-11-181-8/+0
* Move hasFP() and few related hooks to TargetFrameInfo.Anton Korobeynikov2010-11-181-32/+20