| Commit message (Expand) | Author | Age | Files | Lines |
|---|
| ... | |
| * | llvm bug #1350, parts 1, 2, and 3. | Nate Begeman | 2007-05-01 | 1 | -1/+50 |
| * | We'd still like to register allocate r2 on darwin before the callee-save | Nate Begeman | 2007-01-29 | 1 | -6/+6 |
| * | Changes from Nick Lewycky with a simplified PPCTargetAsmInfo. | Jim Laskey | 2006-12-21 | 1 | -2/+6 |
| * | in ppc64-mode, don't allocate the 32-bit version of r13 either. | Chris Lattner | 2006-11-20 | 1 | -0/+6 |
| * | r13 is the thread pointer on darwin/ppc64, don't allocate it. | Chris Lattner | 2006-11-20 | 1 | -3/+3 |
| * | This is a general clean up of the PowerPC ABI. Address several problems and | Jim Laskey | 2006-11-16 | 1 | -2/+2 |
| * | Rework PPC64 calls. Now we have a LR8/CTR8 register which the PPC64 calls | Chris Lattner | 2006-11-14 | 1 | -4/+9 |
| * | Constify some methods. Patch provided by Anton Vayvod, thanks! | Chris Lattner | 2006-08-17 | 1 | -8/+8 |
| * | Remove the -darwin and -aix llc options, inferring darwinism and aixism from | Chris Lattner | 2006-06-16 | 1 | -2/+2 |
| * | Revert Nate's CR patch from last night, which caused many regressions (e.g. f... | Chris Lattner | 2006-05-04 | 1 | -18/+3 |
| * | Since we don't handle callee-save CRs right yet, don't allocate them. Also | Nate Begeman | 2006-05-02 | 1 | -3/+18 |
| * | Prefer to allocate V2-V5 before V0,V1. This lets us generate code like this: | Chris Lattner | 2006-04-17 | 1 | -1/+1 |
| * | add all supported formats to the vector register file | Chris Lattner | 2006-03-25 | 1 | -1/+1 |
| * | Add dwarf register numbering to register data. | Jim Laskey | 2006-03-24 | 1 | -71/+140 |
| * | Claim to have v16i8 for perm masks | Chris Lattner | 2006-03-20 | 1 | -1/+2 |
| * | For functions that use vector registers, save VRSAVE, mark used | Chris Lattner | 2006-03-13 | 1 | -2/+2 |
| * | Bye bye HACKTROCITY. | Evan Cheng | 2005-12-22 | 1 | -8/+0 |
| * | Pattern-match return. Includes gross hack! | Nate Begeman | 2005-12-20 | 1 | -0/+8 |
| * | Add a second vector type to the VRRC register class, and fix some patterns | Nate Begeman | 2005-12-16 | 1 | -3/+3 |
| * | Support multiple ValueTypes per RegisterClass, needed for upcoming vector | Nate Begeman | 2005-12-01 | 1 | -7/+8 |
| * | Cosmetic change, better reflects actual values | Nate Begeman | 2005-12-01 | 1 | -6/+5 |
| * | Add the majority of the vector machien value types we expect to support, | Nate Begeman | 2005-11-29 | 1 | -1/+1 |
| * | don't say this is i128, because it isn't yet. Hopefully nate will change | Chris Lattner | 2005-11-29 | 1 | -1/+1 |
| * | Small tweaks noticed while on the plane. | Nate Begeman | 2005-11-26 | 1 | -1/+1 |
| * | Some first bits of AltiVec stuff: Instruction Formats, Encodings, and | Nate Begeman | 2005-11-23 | 1 | -1/+29 |
| * | apply some tblgen majik to simplify the X register definitions | Chris Lattner | 2005-10-19 | 1 | -19/+19 |
| * | Make a new reg class for 64 bit regs that aliases the 32 bit regs. This | Nate Begeman | 2005-10-19 | 1 | -5/+29 |
| * | First bits of 64 bit PowerPC stuff, currently disabled. A lot of this is | Nate Begeman | 2005-10-18 | 1 | -4/+29 |
| * | Remove an unnecsesary file. PPC32 and PPC64 share architected registers. | Nate Begeman | 2005-10-14 | 1 | -0/+36 |
| * | Remove some regs that are not used. | Chris Lattner | 2005-08-22 | 1 | -7/+0 |
| * | Nate noticed that 30% of the malloc/frees in llc come from calls to Lowercase... | Chris Lattner | 2005-08-22 | 1 | -42/+42 |
| * | Revamp the Register class, and allow the use of the RegisterGroup class to | Chris Lattner | 2004-09-14 | 1 | -29/+49 |
| * | Register classes are target-dependent | Misha Brukman | 2004-08-17 | 1 | -29/+0 |
| * | Fix frame pointer handling: | Nate Begeman | 2004-08-16 | 1 | -3/+6 |
| * | Reenable the CCRC | Chris Lattner | 2004-08-15 | 1 | -1/+2 |
| * | Mark R2 as available for allocation on Darwin/PPC32, but not AIX/PPC64 | Misha Brukman | 2004-08-12 | 1 | -3/+6 |
| * | * Set the is64bit boolean flag in PowerPCRegisterInfo | Misha Brukman | 2004-08-11 | 1 | -3/+3 |
| * | Renamed PPC32 (namespace for regs, opcodes) to PPC to include 64-bit targets | Misha Brukman | 2004-08-10 | 1 | -1/+1 |
| * | Renamed files: | Misha Brukman | 2004-07-27 | 1 | -1/+1 |
| * | LR is a 32-bit int reg | Misha Brukman | 2004-07-27 | 1 | -2/+2 |
| * | * Enable allocation of registers r2-r10 | Misha Brukman | 2004-07-16 | 1 | -4/+7 |
| * | * Do not allocate r0 as we use it indiscriminantly in the instr selector. | Misha Brukman | 2004-07-01 | 1 | -4/+4 |
| * | * Allow more registers to be allocated from the general register pool | Misha Brukman | 2004-06-30 | 1 | -6/+8 |
| * | Only allocate non-volatile registers R13-31 (for now). | Misha Brukman | 2004-06-29 | 1 | -3/+11 |
| * | Initial revision | Misha Brukman | 2004-06-21 | 1 | -0/+82 |
