| Commit message (Expand) | Author | Age | Files | Lines | |
|---|---|---|---|---|---|
| * | Split the LdStGeneral PPC itin. class into LdStLoad and LdStStore. | Hal Finkel | 2012-04-01 | 1 | -1/+2 |
| * | Emacs-tag and some comment fix for all ARM, CellSPU, Hexagon, MBlaze, MSP430,... | Jia Liu | 2012-02-18 | 1 | -3/+3 |
| * | Add support to model pipeline bypass / forwarding. | Evan Cheng | 2010-09-28 | 1 | -1/+1 |
| * | Make processor FUs unique for given itinerary. This extends the limit of 32 | Anton Korobeynikov | 2010-04-18 | 1 | -1/+2 |
| * | Remove attribution from file headers, per discussion on llvmdev. | Chris Lattner | 2007-12-29 | 1 | -2/+2 |
| * | Added InstrSchedClass to each of the PowerPC Instructions. | Jim Laskey | 2005-10-19 | 1 | -3/+3 |
| * | Push processor descriptions to the top of target and add command line info. | Jim Laskey | 2005-10-19 | 1 | -1/+1 |
| * | Simple edits; remove unimplimented cases and clarify long haul SLU cases. | Jim Laskey | 2005-10-18 | 1 | -15/+0 |
| * | Checking in first round of scheduling tablegen files. Not tied in as yet. | Jim Laskey | 2005-10-18 | 1 | -0/+88 |
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