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path: root/lib/Target/R600/R600ISelLowering.cpp
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* R600: Move clamp handling code to R600IselLowering.cppVincent Lejeune2013-09-121-0/+16
* R600: Move code handling literal folding into R600ISelLowering.Vincent Lejeune2013-09-121-4/+59
* R600: Move fabs/fneg/sel folding logic into PostProcessIselVincent Lejeune2013-09-121-0/+179
* R600: Add support for local memory atomic addTom Stellard2013-09-051-7/+15
* R600: Expand SELECT nodes rather than custom lowering themTom Stellard2013-09-051-14/+6
* R600: Add support for vector local memory loadsTom Stellard2013-08-261-0/+8
* R600: Add support for i8 and i16 local memory loadsTom Stellard2013-08-261-14/+15
* R600: Add support for v4i32 and v2i32 local storesTom Stellard2013-08-261-1/+1
* R600: Expand vector float operations for both SI and R600Tom Stellard2013-08-161-9/+0
* R600: Add support for global vector stores with elements less than 32-bitsTom Stellard2013-08-161-1/+7
* R600: Add support for i16 and i8 global storesTom Stellard2013-08-161-12/+49
* R600: Set scheduling preference to Sched::SourceTom Stellard2013-08-121-1/+1
* R600: Add 64-bit float load/store supportTom Stellard2013-08-011-3/+18
* R600/SI: Expand vector fp <-> int conversionsTom Stellard2013-07-301-4/+0
* [R600] Replicate old DAGCombiner behavior in target specific DAG combine.Quentin Colombet2013-07-301-0/+56
* R600: Move CONST_ADDRESS folding into AMDGPUDAGToDAGISel::Select()Tom Stellard2013-07-231-0/+24
* R600: Use KCache for kernel argumentsTom Stellard2013-07-231-31/+11
* R600: Use the same compute kernel calling convention for all GPUsTom Stellard2013-07-231-6/+15
* R600: Use correct LoadExtType when lowering kernel argumentsTom Stellard2013-07-231-1/+9
* R600: Clean up extended load patternsTom Stellard2013-07-231-4/+4
* R600: Expand VSELECT for all typesTom Stellard2013-07-181-3/+0
* R600/SI: Initial local memory supportMichel Danzer2013-07-101-0/+2
* R600: Fix a rare bug where swizzle optimization returns wrong valuesVincent Lejeune2013-07-091-2/+3
* R600: Use DAG lowering pass to handle fcos/fsinVincent Lejeune2013-07-091-1/+38
* R600: Add local memory support via LDSTom Stellard2013-06-281-2/+16
* R600: Use new getNamedOperandIdx function generated by TableGenTom Stellard2013-06-251-1/+1
* R600: Consolidate expansion of v2i32/v4i32 ops for EG/SIAaron Watry2013-06-251-19/+0
* R600/SI: Expand udiv v[24]i32 for SI and v2i32 for EGAaron Watry2013-06-251-0/+1
* R600: Expand v2i32 load/store instead of custom loweringTom Stellard2013-06-201-2/+2
* R600: Make helper functions static.Benjamin Kramer2013-06-111-4/+5
* Don't cache the instruction and register info from the TargetMachine, becauseBill Wendling2013-06-071-2/+6
* R600: Swizzle texture/export instructionsVincent Lejeune2013-06-041-20/+125
* R600: Constraints input regs of interp_xy,_zwVincent Lejeune2013-06-031-9/+13
* Track IR ordering of SelectionDAG nodes 2/4.Andrew Trick2013-05-251-17/+17
* R600ISelLowering.cpp: Avoid "using namespace Intrinsic;" to appease MSC. Spec...NAKAMURA Takumi2013-05-221-18/+15
* R600: Whitespace and untabify.NAKAMURA Takumi2013-05-221-2/+2
* R600: Swap the legality of rotl and rotrTom Stellard2013-05-201-15/+0
* Add LLVMContext argument to getSetCCResultTypeMatt Arsenault2013-05-181-1/+1
* R600: Lower int_load_input to copyFromReg instead of Register nodeVincent Lejeune2013-05-171-1/+5
* R600: Relax some vector constraints on Dot4.Vincent Lejeune2013-05-171-0/+21
* R600: Improve texture handlingVincent Lejeune2013-05-171-19/+241
* R600: Expand SUB for v2i32/v4i32Tom Stellard2013-05-101-0/+2
* R600: Expand MUL for v4i32/v2i32Tom Stellard2013-05-101-0/+2
* R600: Expand SRA for v4i32/v2i32Tom Stellard2013-05-101-0/+2
* R600: Expand vselect for v4i32 and v2i32Tom Stellard2013-05-101-0/+3
* R600: Expand vector or, shl, srl, and xor nodesTom Stellard2013-05-031-0/+8
* R600: Initialize BooleanVectorContentsTom Stellard2013-04-241-0/+1
* R600/SI: add mulhu/mulhs patternsChristian Konig2013-03-271-1/+0
* R600: Use legacy (0 * anything = 0) MUL instructions for pow intrinsicsMichel Danzer2013-03-221-11/+0
* R600: Fix JUMP handling so that MachineInstr verification can occurVincent Lejeune2013-03-111-4/+3
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