external_llvm.git - Unnamed repository; edit this file 'description' to name the repository.

	Commit message (Expand)	Author	Age	Files	Lines
*	Update aosp/master llvm for rebase to r233350	Pirama Arumuga Nainar	2015-04-09	1	-9/+5
*	Update aosp/master LLVM for rebase to r222494.	Stephen Hines	2014-12-02	1	-18/+17
*	Update LLVM for rebase to r212749.	Stephen Hines	2014-07-21	1	-22/+68
*	Update LLVM for 3.5 rebase (r209712).	Stephen Hines	2014-05-29	1	-4/+4
*	Update to LLVM 3.5a.	Stephen Hines	2014-04-24	1	-2/+8
*	Merging r195399:	Bill Wendling	2013-11-22	1	-0/+12
*	[weak vtables] Remove a bunch of weak vtables	Juergen Ributzka	2013-11-19	1	-1/+1
*	Revert r194865 and r194874.	Alexey Samsonov	2013-11-18	1	-1/+1
*	R600: Make dot_4 instructions predicable	Vincent Lejeune	2013-11-16	1	-0/+19
*	[weak vtables] Remove a bunch of weak vtables	Juergen Ributzka	2013-11-15	1	-1/+1
*	R600: Fix scheduling of instructions that use the LDS output queue	Tom Stellard	2013-11-15	1	-0/+8
*	R600/SI: Add support for private address space load/store	Tom Stellard	2013-11-13	1	-47/+5
*	R600: Simplify handling of private address space	Tom Stellard	2013-10-22	1	-11/+16
*	R600: Remove unused InstrInfo::getMovImmInstr() function	Tom Stellard	2013-10-22	1	-12/+0
*	R600: add a pass that merges clauses.	Vincent Lejeune	2013-10-01	1	-0/+18
*	R600: Enable -verify-machineinstrs in some tests.	Vincent Lejeune	2013-10-01	1	-0/+9
*	IfConverter: Use TargetSchedule for instruction latencies	Arnold Schwaighofer	2013-09-30	1	-0/+4
*	R600: Don't use trans slot for instructions that read LDS source registers	Tom Stellard	2013-09-12	1	-0/+16
*	R600: Use shared op optimization when checking cycle compatibility	Vincent Lejeune	2013-09-04	1	-0/+2
*	R600: Non vector only instruction can be scheduled on trans unit	Vincent Lejeune	2013-09-04	1	-0/+3
*	R600: Use SchedModel enum for is{Trans,Vector}Only functions	Vincent Lejeune	2013-09-04	1	-1/+11
*	R600: Add support for i8 and i16 local memory stores	Tom Stellard	2013-08-26	1	-1/+2
*	R600: Add IsExport bit to TableGen instruction definitions	Tom Stellard	2013-08-16	1	-0/+4
*	R600: Add 64-bit float load/store support	Tom Stellard	2013-08-01	1	-8/+11
*	Revert "R600: Non vector only instruction can be scheduled on trans unit"	Tom Stellard	2013-07-31	1	-3/+0
*	Revert "R600: Use SchedModel enum for is{Trans,Vector}Only functions"	Tom Stellard	2013-07-31	1	-11/+1
*	R600: Avoid more than 4 literals in the same instruction group at scheduling	Vincent Lejeune	2013-07-31	1	-0/+5
*	R600: Non vector only instruction can be scheduled on trans unit	Vincent Lejeune	2013-07-31	1	-0/+3
*	R600: Use SchedModel enum for is{Trans,Vector}Only functions	Vincent Lejeune	2013-07-31	1	-1/+11
*	R600: Move CONST_ADDRESS folding into AMDGPUDAGToDAGISel::Select()	Tom Stellard	2013-07-23	1	-0/+36
*	Use SmallVectorImpl& instead of SmallVector to avoid repeating small vector s...	Craig Topper	2013-07-14	1	-1/+1
*	Replacing an empty switch with its moral equivalent. No functional changes i...	Aaron Ballman	2013-07-10	1	-3/+1
*	R600: Do not predicated basic block with multiple alu clause	Vincent Lejeune	2013-07-09	1	-0/+45
*	R600: Fix an unitialized variable in R600InstrInfo.cpp	Vincent Lejeune	2013-06-30	1	-1/+1
*	R600: Unbreak GCC build.	Benjamin Kramer	2013-06-29	1	-1/+2
*	R600: Support schedule and packetization of trans-only inst	Vincent Lejeune	2013-06-29	1	-39/+146
*	R600: Bank Swizzle now display SCL equivalent	Vincent Lejeune	2013-06-29	1	-4/+4
*	R600: Add local memory support via LDS	Tom Stellard	2013-06-28	1	-8/+38
*	R600: Add support for GROUP_BARRIER instruction	Tom Stellard	2013-06-28	1	-0/+10
*	R600: Add ALUInst bit to tablegen definitions v2	Tom Stellard	2013-06-28	1	-3/+1
*	R600: Use new getNamedOperandIdx function generated by TableGen	Tom Stellard	2013-06-25	1	-116/+74
*	R600: PV stores Reg id, not index	Vincent Lejeune	2013-06-17	1	-1/+1
*	R600: Rework subtarget info and remove AMDILDevice classes	Tom Stellard	2013-06-07	1	-1/+1
*	Don't cache the instruction and register info from the TargetMachine, because	Bill Wendling	2013-06-07	1	-1/+1
*	R600: Make sure to schedule AR register uses and defs in the same clause	Tom Stellard	2013-06-05	1	-2/+4
*	R600: Const/Neg/Abs can be folded to dot4	Vincent Lejeune	2013-06-04	1	-0/+35
*	Move passes from namespace llvm into anonymous namespaces. Sort includes whil...	Benjamin Kramer	2013-05-23	1	-1/+1
*	R600: Relax some vector constraints on Dot4.	Vincent Lejeune	2013-05-17	1	-3/+89
*	R600: Some factorization	Vincent Lejeune	2013-05-17	1	-24/+162
*	R600: Remove dead code from the CodeEmitter v2	Tom Stellard	2013-05-06	1	-3/+2