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Target
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R600
/
R600InstrInfo.h
Commit message (
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Author
Age
Files
Lines
*
R600: Support schedule and packetization of trans-only inst
Vincent Lejeune
2013-06-29
1
-10
/
+22
*
R600: Bank Swizzle now display SCL equivalent
Vincent Lejeune
2013-06-29
1
-5
/
+5
*
R600: Add local memory support via LDS
Tom Stellard
2013-06-28
1
-0
/
+11
*
R600: Add support for GROUP_BARRIER instruction
Tom Stellard
2013-06-28
1
-0
/
+2
*
R600: Use new getNamedOperandIdx function generated by TableGen
Tom Stellard
2013-06-25
1
-5
/
+3
*
R600: Rework subtarget info and remove AMDILDevice classes
Tom Stellard
2013-06-07
1
-1
/
+0
*
R600: Const/Neg/Abs can be folded to dot4
Vincent Lejeune
2013-06-04
1
-0
/
+2
*
R600: Relax some vector constraints on Dot4.
Vincent Lejeune
2013-05-17
1
-0
/
+5
*
R600: Some factorization
Vincent Lejeune
2013-05-17
1
-0
/
+28
*
R600: Rework Scheduling to handle difference between VLIW4 and VLIW5 chips
Vincent Lejeune
2013-04-30
1
-0
/
+3
*
R600: Add FetchInst bit to instruction defs to denote vertex/tex instructions
Vincent Lejeune
2013-04-30
1
-0
/
+6
*
R600: Factorize maximum alu per clause in a single location
Vincent Lejeune
2013-04-03
1
-0
/
+1
*
R600: Factorize code handling Const Read Port limitation
Vincent Lejeune
2013-03-14
1
-0
/
+3
*
R600: Support for indirect addressing v4
Tom Stellard
2013-02-06
1
-0
/
+32
*
Resort the #include lines in include/... and lib/... with the
Chandler Carruth
2013-01-02
1
-2
/
+1
*
Add R600 backend
Tom Stellard
2012-12-11
1
-0
/
+169