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	Commit message (Collapse)	Author	Age	Files	Lines
*	R600/SI: Lower BUILD_VECTOR to REG_SEQUENCE v2	Tom Stellard	2013-08-14	1	-4/+0
\| \| \| \| \| \| \| \| \| \| \| \|	Using REG_SEQUENCE for BUILD_VECTOR rather than a series of INSERT_SUBREG instructions should make it easier for the register allocator to coalasce unnecessary copies. v2: - Use an SGPR register class if all the operands of BUILD_VECTOR are SGPRs. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@188427 91177308-0d34-0410-b5e6-96231b3b80d8
*	Don't cache the instruction and register info from the TargetMachine, because	Bill Wendling	2013-06-07	1	-3/+1
\| \| \| \| \| \| \| \| \|	the internals of TargetMachine could change. No functionality change intended. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183561 91177308-0d34-0410-b5e6-96231b3b80d8
*	R600: Use bottom up scheduling algorithm	Vincent Lejeune	2013-05-17	1	-0/+3
\| \| \| \|	git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182129 91177308-0d34-0410-b5e6-96231b3b80d8
*	Resort the #include lines in include/... and lib/... with the	Chandler Carruth	2013-01-02	1	-1/+1
\| \| \| \| \| \| \| \| \| \|	utils/sort_includes.py script. Most of these are updating the new R600 target and fixing up a few regressions that have creeped in since the last time I sorted the includes. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@171362 91177308-0d34-0410-b5e6-96231b3b80d8
*	Add R600 backend	Tom Stellard	2012-12-11	1	-0/+55
	A new backend supporting AMD GPUs: Radeon HD2XXX - HD7XXX git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@169915 91177308-0d34-0410-b5e6-96231b3b80d8