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* R600: Improve asmPrint of ALU clauseVincent Lejeune2013-05-023-4/+20
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@180957 91177308-0d34-0410-b5e6-96231b3b80d8
* R600: Prettier asmPrint of AluVincent Lejeune2013-05-024-13/+45
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@180956 91177308-0d34-0410-b5e6-96231b3b80d8
* R600: Use new tablegen syntax for patternsTom Stellard2013-05-023-447/+381
| | | | | | | | All but two patterns have been converted to the new syntax. The remaining two patterns will require COPY_TO_REGCLASS instructions, which the VLIW DAG Scheduler cannot handle. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@180922 91177308-0d34-0410-b5e6-96231b3b80d8
* R600/SI: remove nonsense select patternTom Stellard2013-05-021-8/+1
| | | | | | | | | Fortunately this pattern never matched, otherwise we would have generated incorrect code. Signed-off-by: Christian K??nig <christian.koenig@amd.com> git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@180921 91177308-0d34-0410-b5e6-96231b3b80d8
* R600: Always use texture cache for compute shadersVincent Lejeune2013-04-301-2/+6
| | | | | | This will improve the performance of memory reads. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@180762 91177308-0d34-0410-b5e6-96231b3b80d8
* R600: use native for aluVincent Lejeune2013-04-304-4/+135
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@180761 91177308-0d34-0410-b5e6-96231b3b80d8
* R600: Packetize instructionsVincent Lejeune2013-04-306-3/+464
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@180760 91177308-0d34-0410-b5e6-96231b3b80d8
* R600: Rework Scheduling to handle difference between VLIW4 and VLIW5 chipsVincent Lejeune2013-04-305-32/+105
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@180759 91177308-0d34-0410-b5e6-96231b3b80d8
* R600: Add a Bank Swizzle operandVincent Lejeune2013-04-304-11/+19
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@180758 91177308-0d34-0410-b5e6-96231b3b80d8
* R600: Take inner dependency into tex/vtx clausesVincent Lejeune2013-04-301-0/+34
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@180757 91177308-0d34-0410-b5e6-96231b3b80d8
* R600: Turn TEX/VTX into native instructionsVincent Lejeune2013-04-303-15/+50
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@180756 91177308-0d34-0410-b5e6-96231b3b80d8
* R600: Add FetchInst bit to instruction defs to denote vertex/tex instructionsVincent Lejeune2013-04-309-58/+95
| | | | | | v2[Vincent Lejeune]: Split FetchInst into usesTextureCache/usesVertexCache git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@180755 91177308-0d34-0410-b5e6-96231b3b80d8
* R600: Add some new processor variantsVincent Lejeune2013-04-302-1/+3
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@180753 91177308-0d34-0410-b5e6-96231b3b80d8
* R600: Clean up instruction class definitionsVincent Lejeune2013-04-301-23/+14
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@180752 91177308-0d34-0410-b5e6-96231b3b80d8
* R600: config section now reports use of killgtVincent Lejeune2013-04-301-0/+4
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@180751 91177308-0d34-0410-b5e6-96231b3b80d8
* R600: Use correct CF_END instruction on Northern Island GPUsTom Stellard2013-04-291-1/+1
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@180735 91177308-0d34-0410-b5e6-96231b3b80d8
* R600: Fix encoding of CF_END_{EG, R600} instructionsTom Stellard2013-04-291-0/+1
| | | | | | The EOP bit was not being encoded. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@180734 91177308-0d34-0410-b5e6-96231b3b80d8
* R600: Initialize AMDGPUMachineFunction::ShaderType to ShaderType::COMPUTETom Stellard2013-04-261-0/+2
| | | | | | | | | | We need to intialize this to something and since clang does not set the shader type attribute and clang is used only for compute shaders, initializing it to COMPUTE seems like the best choice. Reviewed-by: Christian König <christian.koenig@amd.com> git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@180620 91177308-0d34-0410-b5e6-96231b3b80d8
* R600: Initialize BooleanVectorContentsTom Stellard2013-04-241-0/+1
| | | | | | Fixes test/CodeGen/R600/setcc.ll git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@180231 91177308-0d34-0410-b5e6-96231b3b80d8
* R600: Use SHT_PROGBITS for the .AMDGPU.config sectionTom Stellard2013-04-241-1/+1
| | | | | | | | The libelf implementation that is distributed here: http://www.mr511.de/software/english.html will not parse sections that are marked SHT_NULL. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@180230 91177308-0d34-0410-b5e6-96231b3b80d8
* R600: Use .AMDGPU.config section to emit stacksizeVincent Lejeune2013-04-235-16/+25
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@180124 91177308-0d34-0410-b5e6-96231b3b80d8
* R600: Add CF_ENDVincent Lejeune2013-04-233-44/+77
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@180123 91177308-0d34-0410-b5e6-96231b3b80d8
* Remove unused DwarfSectionOffsetDirective stringMatt Arsenault2013-04-221-2/+0
| | | | | | | The value isn't actually used, and setting it emits a COFF specific directive. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@180064 91177308-0d34-0410-b5e6-96231b3b80d8
* ArrayRefize getMachineNode(). No functionality change.Michael Liao2013-04-192-2/+2
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179901 91177308-0d34-0410-b5e6-96231b3b80d8
* R600: Add pattern for the BFI_INT instructionTom Stellard2013-04-193-0/+24
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179830 91177308-0d34-0410-b5e6-96231b3b80d8
* R600/SI: Use InstFlag for VOP3 modifier operandsTom Stellard2013-04-192-15/+14
| | | | | | | | InstFlag has a default value of 0 and will simplify the VOP3 patterns. Reviewed-by: Michel Dänzer <michel.daenzer@amd.com> git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179829 91177308-0d34-0410-b5e6-96231b3b80d8
* R600: Make Export Instruction not duplicableVincent Lejeune2013-04-171-1/+3
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179686 91177308-0d34-0410-b5e6-96231b3b80d8
* R600: Export is emitted as a CF_NATIVE instVincent Lejeune2013-04-172-14/+9
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179685 91177308-0d34-0410-b5e6-96231b3b80d8
* R600: Emit used GPRs countVincent Lejeune2013-04-172-8/+41
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179684 91177308-0d34-0410-b5e6-96231b3b80d8
* R600/SI: Emit config values in register value pairs.Tom Stellard2013-04-152-3/+38
| | | | | | | | Instead of emitting config values in a predefined order, the code emitter will now emit a 32-bit register index followed by the 32-bit config value. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179546 91177308-0d34-0410-b5e6-96231b3b80d8
* R600/SI: Emit configuration value in the .AMDGPU.config ELF sectionTom Stellard2013-04-151-1/+9
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179545 91177308-0d34-0410-b5e6-96231b3b80d8
* R600: Emit ELF formatted code rather than raw ISA.Tom Stellard2013-04-155-12/+63
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179544 91177308-0d34-0410-b5e6-96231b3b80d8
* R600ControlFlowFinalizer.cpp: Fix a warning. [-Wunused-variable]NAKAMURA Takumi2013-04-111-0/+1
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179263 91177308-0d34-0410-b5e6-96231b3b80d8
* Whitespace.NAKAMURA Takumi2013-04-111-2/+1
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179262 91177308-0d34-0410-b5e6-96231b3b80d8
* R600/SI: Add pattern for AMDGPUurecipMichel Danzer2013-04-103-3/+13
| | | | | | | | 21 more little piglits with radeonsi. Reviewed-by: Tom Stellard <thomas.stellard@amd.com> git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179186 91177308-0d34-0410-b5e6-96231b3b80d8
* R600: Add VTX_READ_* and RAT_WRITE_CACHELESS_* when computing cf addrVincent Lejeune2013-04-101-1/+10
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179174 91177308-0d34-0410-b5e6-96231b3b80d8
* R600/SI: dynamical figure out the reg class of MIMGChristian Konig2013-04-106-2/+63
| | | | | | | | | Depending on the number of bits set in the writemask. Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Michel Dänzer <michel.daenzer@amd.com> git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179166 91177308-0d34-0410-b5e6-96231b3b80d8
* R600/SI: adjust writemask to only the used componentsChristian Konig2013-04-104-2/+91
| | | | | | | Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Michel Dänzer <michel.daenzer@amd.com> git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179165 91177308-0d34-0410-b5e6-96231b3b80d8
* R600/SI: remove image sample writemaskChristian Konig2013-04-102-14/+13
| | | | | | | Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Michel Dänzer <michel.daenzer@amd.com> git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179164 91177308-0d34-0410-b5e6-96231b3b80d8
* R600: Control Flow support for pre EG genVincent Lejeune2013-04-083-72/+240
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179020 91177308-0d34-0410-b5e6-96231b3b80d8
* R600/SI: Add support for buffer stores v2Tom Stellard2013-04-058-4/+99
| | | | | | | | | v2: - Use the ADDR64 bit Reviewed-by: Christian König <christian.koenig@amd.com> git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178931 91177308-0d34-0410-b5e6-96231b3b80d8
* R600/SI: Use same names for corresponding MUBUF operands and encoding fieldsTom Stellard2013-04-052-27/+27
| | | | | | | | | | | | The code emitter knows how to encode operands whose name matches one of the encoding fields. If there is no match, the code emitter relies on the order of the operand and field definitions to determine how operands should be encoding. Matching by order makes it easy to accidentally break the instruction encodings, so we prefer to match by name. Reviewed-by: Christian König <christian.koenig@amd.com> git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178930 91177308-0d34-0410-b5e6-96231b3b80d8
* R600: Add RV670 processorTom Stellard2013-04-051-0/+1
| | | | | | | | This is an R600 GPU with double support. Reviewed-by: Christian König <christian.koenig@amd.com> git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178929 91177308-0d34-0410-b5e6-96231b3b80d8
* R600/SI: Add processor types for each SI variantTom Stellard2013-04-052-3/+8
| | | | | | Reviewed-by: Christian König <christian.koenig@amd.com> git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178928 91177308-0d34-0410-b5e6-96231b3b80d8
* R600/SI: Avoid generating S_MOVs with 64-bit immediates v2Tom Stellard2013-04-051-2/+5
| | | | | | | | | | | | | | SITargetLowering::analyzeImmediate() was converting the 64-bit values to 32-bit and then checking if they were an inline immediate. Some of these conversions caused this check to succeed and produced S_MOV instructions with 64-bit immediates, which are illegal. v2: - Clean up logic Reviewed-by: Christian König <christian.koenig@amd.com> git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178927 91177308-0d34-0410-b5e6-96231b3b80d8
* R600: Use a mask for offsets when encoding instructionsVincent Lejeune2013-04-041-2/+5
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178763 91177308-0d34-0410-b5e6-96231b3b80d8
* R600: Fix wrong address when substituting ENDIFVincent Lejeune2013-04-041-1/+1
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178762 91177308-0d34-0410-b5e6-96231b3b80d8
* R600: Take export into account when computing cf addressVincent Lejeune2013-04-041-0/+4
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178761 91177308-0d34-0410-b5e6-96231b3b80d8
* R600: Fix last ALU of a clause being emitted in a separate clauseVincent Lejeune2013-04-031-2/+2
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178675 91177308-0d34-0410-b5e6-96231b3b80d8
* R600: Factorize maximum alu per clause in a single locationVincent Lejeune2013-04-034-2/+6
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178667 91177308-0d34-0410-b5e6-96231b3b80d8
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