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* Use SmallVectorImpl::iterator/const_iterator instead of SmallVector to avoid ...Craig Topper2013-07-031-12/+12
* Remove address spaces from MC.Rafael Espindola2013-07-022-6/+0
* Add a newline.Chad Rosier2013-07-011-1/+1
* R600: Fix an unitialized variable in R600InstrInfo.cppVincent Lejeune2013-06-301-1/+1
* R600: Unbreak GCC build.Benjamin Kramer2013-06-291-1/+2
* R600: Support schedule and packetization of trans-only instVincent Lejeune2013-06-297-90/+246
* R600: Bank Swizzle now display SCL equivalentVincent Lejeune2013-06-293-12/+12
* R600/SI: Add processor types for each CIK variantTom Stellard2013-06-281-0/+3
* R600: Add local memory support via LDSTom Stellard2013-06-2817-24/+254
* R600: Add support for GROUP_BARRIER instructionTom Stellard2013-06-287-3/+64
* R600: Add ALUInst bit to tablegen definitions v2Tom Stellard2013-06-284-4/+8
* R600: Use new getNamedOperandIdx function generated by TableGenTom Stellard2013-06-2510-228/+160
* R600: Consolidate expansion of v2i32/v4i32 ops for EG/SIAaron Watry2013-06-253-49/+22
* R600/SI: Expand xor v2i32/v4i32Aaron Watry2013-06-251-0/+3
* R600/SI: Expand urem of v2i32/v4i32 for SIAaron Watry2013-06-251-0/+3
* R600/SI: Expand udiv v[24]i32 for SI and v2i32 for EGAaron Watry2013-06-252-0/+4
* R600/SI: Expand ashr of v2i32/v4i32 for SIAaron Watry2013-06-251-0/+2
* R600/SI: Expand srl of v2i32/v4i32 for SIAaron Watry2013-06-251-0/+2
* R600/SI: Expand shl of v2i32/v4i32 for SIAaron Watry2013-06-251-0/+3
* R600/SI: Expand or of v2i32/v4i32 for SIAaron Watry2013-06-251-0/+3
* R600/SI: Expand mul of v2i32/v4i32 for SIAaron Watry2013-06-251-0/+3
* R600/SI: Expand and of v2i32/v4i32 for SIAaron Watry2013-06-251-0/+3
* R600/SI: Report unaligned memory accesses as legal for > 32-bit typesTom Stellard2013-06-252-0/+13
* R600: Add support for i32 loads from the constant address space on CaymanTom Stellard2013-06-251-0/+9
* R600/SI: Add support for v4i32 and v4f32 kernel argsTom Stellard2013-06-251-4/+5
* R600: Fix typo in R600Schedule.tdTom Stellard2013-06-251-2/+2
* R600: Fix spelling error in commentAaron Watry2013-06-241-1/+1
* R600/SI: Expand sub for v2i32 and v4i32 for SITom Stellard2013-06-201-0/+3
* R600/SI: Expand add for v2i32 and v4i32Tom Stellard2013-06-201-0/+2
* R600: Expand v2i32 load/store instead of custom loweringTom Stellard2013-06-201-2/+2
* Access the TargetLoweringInfo from the TargetMachine object instead of cachin...Bill Wendling2013-06-192-4/+5
* Move StructurizeCFG out of R600 to generic Transforms.Matt Arsenault2013-06-193-898/+1
* Use GetUnderlyingObject instead of custom functionMatt Arsenault2013-06-181-58/+20
* Remove dead prototype.Bill Wendling2013-06-181-2/+0
* R600: PV stores Reg id, not indexVincent Lejeune2013-06-171-1/+1
* R600: Properly set COUNT_3 bit in TEX clause initiating inst for pre EG gen.Vincent Lejeune2013-06-171-14/+16
* R600: Add SI load support for v[24]i32 and store for v2i32Tom Stellard2013-06-151-0/+5
* R600: Use correct encoding for Vertex Fetch instructions on CaymanTom Stellard2013-06-143-156/+294
* R600: Use EXPORT_RAT_INST_STORE_DWORD for stores on CaymanTom Stellard2013-06-142-37/+57
* R600: Factor the instruction encoding out the RAT_WRITE_CACHELESS_eg classTom Stellard2013-06-142-50/+68
* R600: Move instruction encoding definitions into a separate .td fileTom Stellard2013-06-142-362/+393
* R600: Don't try to fix reg class when copying IMPLICIT_DEF to a registerTom Stellard2013-06-131-1/+2
* R600: Make helper functions static.Benjamin Kramer2013-06-111-4/+5
* R600: Use a refined heuristic to choose when switching clauseVincent Lejeune2013-06-072-10/+47
* R600: Anti dep better handled in tex clauseVincent Lejeune2013-06-071-6/+4
* R600: Fix calculation of stack offset in AMDGPUFrameLoweringTom Stellard2013-06-071-21/+2
* R600: Rework subtarget info and remove AMDILDevice classesTom Stellard2013-06-0736-1458/+218
* Don't cache the instruction and register info from the TargetMachine, becauseBill Wendling2013-06-0721-63/+75
* R600: Fix the fetch limits for R600 generation GPUsTom Stellard2013-06-074-27/+30
* R600: Move Subtarget feature definitions into AMDGPU.tdTom Stellard2013-06-072-64/+66