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* R600/SI: rework VOP3 classesChristian Konig2013-02-211-14/+14
* R600/SI: simplify VOPC_* pattern v2Christian Konig2013-02-213-255/+217
* R600/SI: rework VOP2_* pattern v2Christian Konig2013-02-212-21/+19
* R600/SI: rework VOP1_* patterns v2Christian Konig2013-02-211-17/+21
* R600/SI: add constant for inline zero operandChristian Konig2013-02-211-4/+3
* R600/SI: cleanup SIInstrInfo.td and SIInstrFormat.tdChristian Konig2013-02-212-488/+527
* R600: Fix for Unigine when MachineSched is enabledTom Stellard2013-02-211-0/+1
* R600/SI: Make sure M0 is loaded for V_INTERP_MOV_F32Michel Danzer2013-02-211-1/+2
* R600: Update for name changes from r175667.Jim Grosbach2013-02-201-3/+3
* R600: Add AR_X to the R600_TReg_X register class.Tom Stellard2013-02-191-1/+1
* R600: Mark all members of the TRegMem register class as reservedTom Stellard2013-02-191-0/+6
* R600: Fix scheduler crash caused by invalid MachinePointerInfoTom Stellard2013-02-191-1/+1
* R600: Fix tracking of implicit defs in the IndirectAddressing passTom Stellard2013-02-191-7/+25
* Use LLVM_DELETED_FUNCTION rather than '// do not implement' comments.David Blaikie2013-02-182-4/+4
* R600/SI: Use MULADD_IEEE/V_MAD_F32 instruction for mad patternVincent Lejeune2013-02-187-23/+15
* R600: Support for TBOVincent Lejeune2013-02-183-1/+58
* R600: Increase number of ArrayBase Reg to 32Vincent Lejeune2013-02-181-2/+2
* Target/R600/CMakeLists.txt: Prune SILowerLiteralConstants.cpp corresponding t...NAKAMURA Takumi2013-02-161-1/+0
* R600/SI: Add pattern to simplify i64 loadingChristian Konig2013-02-162-0/+9
* R600/SI: nuke SReg_1 v3Christian Konig2013-02-167-118/+23
* R600/SI: cleanup literal handling v3Christian Konig2013-02-1610-195/+176
* R600/SI: replace AllReg_* with [SV]Src_* v2Christian Konig2013-02-163-85/+89
* R600/SI: fix VOPC encoding v2Christian Konig2013-02-161-37/+16
* R600/SI: move *_Helper definitions to SIInstrFormat.tdChristian Konig2013-02-162-66/+66
* R600/SI: remove some more unused codeChristian Konig2013-02-162-52/+0
* R600/structurizer: improve inverting conditionsChristian Konig2013-02-161-1/+39
* R600/structurizer: improve loop handlingChristian Konig2013-02-161-196/+148
* R600/structurizer: improve finding condition valuesChristian Konig2013-02-161-9/+22
* R600/structurizer: improve PHI value findingChristian Konig2013-02-161-0/+6
* R600/structurizer: add class to find the Nearest Common DominatorChristian Konig2013-02-161-0/+66
* R600/SI: Fix int_SI_fs_interp_constantMichel Danzer2013-02-145-37/+34
* R600: Do not fold single instruction with more that 3 kcache readVincent Lejeune2013-02-142-1/+3
* R600: Export instructions are no longer terminatorVincent Lejeune2013-02-141-2/+2
* R600: Fold zero/one in export instructionsVincent Lejeune2013-02-143-80/+55
* R600: Do not fold modifier/litterals in vector instVincent Lejeune2013-02-141-2/+5
* R600/SI: Check for empty stack in SIAnnotateControlFlow::isTopOfStackMichel Danzer2013-02-141-1/+1
* R600: Add support for 128-bit parametersTom Stellard2013-02-132-0/+5
* R600: Fix regression with shadow array sampler on pre-SI GPUs.Michel Danzer2013-02-121-1/+1
* R600/SI: Use V_ADD_F32 instead of V_MOV_B32 for clamp/neg/abs modifiers.Michel Danzer2013-02-111-15/+9
* Test Commit - Remove some trailing whitespace in R600Instructions.tdVincent Lejeune2013-02-101-6/+6
* R600: Dump the function name when TargetLowering::LowerCall() failsTom Stellard2013-02-081-0/+5
* R600: rework flow creation in the structurizer v2Tom Stellard2013-02-081-177/+195
* R600: fix loop analyses in the structurizerTom Stellard2013-02-081-113/+183
* R600: fix PHI value adding in the structurizerTom Stellard2013-02-081-65/+81
* R600/SI: cleanup VGPR encodingTom Stellard2013-02-075-178/+16
* R600/SI: Handle VGPR64 destination in copyPhysReg().Tom Stellard2013-02-071-1/+9
* R600/SI: Add pattern for mul.Tom Stellard2013-02-071-0/+4
* R600/SI: simplify and fix SMRD encodingTom Stellard2013-02-076-154/+70
* R600/SI: add proper 64bit immediate support v2Tom Stellard2013-02-073-12/+18
* R600: Add an explicit default processorTom Stellard2013-02-071-0/+1
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