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path: root/lib/Target/Sparc/SparcInstrInfo.td
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* remove redundant/dead varsChris Lattner2006-11-031-2/+0
* Merge ISD::TRUNCSTORE to ISD::STORE. Switch to using StoreSDNode.Evan Cheng2006-10-131-6/+6
* adjcallstackup/down clobbers the stack pointerChris Lattner2006-10-121-2/+2
* Add properties to ComplexPattern.Evan Cheng2006-10-111-2/+2
* Reflects ISD::LOAD / ISD::LOADX / LoadSDNode changes.Evan Cheng2006-10-091-16/+16
* Use a couple of multiclass patterns to factor some integer ops.Chris Lattner2006-09-011-135/+49
* remove a bunch of commentsChris Lattner2006-09-011-54/+0
* CALLSEQ_* produces chain even if that's not needed.Evan Cheng2006-08-111-2/+4
* Some notes and thoughts to myselfChris Lattner2006-05-091-7/+7
* The HasNoV9 hack isn't needed here, now that tblgen knows that CustomDAGSched...Chris Lattner2006-02-211-3/+2
* kill ADD_PARTS & SUB_PARTS and replace them with fancy new ADDC, ADDE, SUBCNate Begeman2006-02-171-6/+18
* Use the auto-generated call matcher. Remove a broken impl of the frameaddr/r...Chris Lattner2006-02-101-4/+10
* Update to new-style flags usage, simplifying the .td fileChris Lattner2006-02-101-27/+25
* add an option to turn on LSR.Chris Lattner2006-02-091-0/+56
* Rename SPARC V8 target to be the LLVM SPARC target.Chris Lattner2006-02-051-74/+74
* %fcc is not an alias for %fcc0Chris Lattner2006-02-021-4/+4
* correct an opcodeChris Lattner2006-02-021-2/+2
* add conditional moves of float and double values on int/fp condition codes.Chris Lattner2006-01-311-6/+27
* treat conditional branches the same way as conditional moves (giving themChris Lattner2006-01-311-92/+11
* compactify all of the integer conditional moves into one instruction that takesChris Lattner2006-01-311-88/+25
* Add immediate forms of integer cmovsChris Lattner2006-01-311-6/+49
* ShrinkifyChris Lattner2006-01-311-143/+86
* Add the full complement of conditional moves of integer registers.Chris Lattner2006-01-311-7/+115
* Revamp the ICC/FCC reading instructions to be parameterized in terms of theChris Lattner2006-01-301-30/+81
* Compile:Chris Lattner2006-01-301-0/+8
* When in v9 mode, emit fabsd/fnegd/fmovdChris Lattner2006-01-301-8/+30
* First step towards V9 instructions in the V8 backend, two conditional moveChris Lattner2006-01-301-0/+36
* Use V8ISD::CALL instead of ISD::CALLChris Lattner2006-01-271-1/+1
* PHI and INLINEASM are now built-in instructions provided by Target.tdChris Lattner2006-01-271-1/+0
* Don't print a label for the first MBB in a function.Chris Lattner2006-01-151-0/+7
* Fix branches on FP comparesChris Lattner2006-01-121-3/+2
* Use Evan's outflag stuff to implement V8cmpicc. This allows us to write aChris Lattner2006-01-111-5/+6
* Unbreak ret void :-/Chris Lattner2006-01-111-0/+1
* Write this pattern in canonical form, allowing more patterns to match.Chris Lattner2006-01-111-1/+1
* New DAG node properties SNDPInFlag, SNDPOutFlag, and SNDPOptInFlag to replaceEvan Cheng2006-01-091-11/+6
* Added field noResults to Instruction.Evan Cheng2005-12-261-2/+4
* * Removed the use of FLAG. Now use hasFlagIn and hasFlagOut instead.Evan Cheng2005-12-231-13/+21
* fix the int<->fp instructions, which apparently take a single float registerChris Lattner2005-12-231-6/+10
* clean up .td file by using evan's new FLAG thingChris Lattner2005-12-221-4/+4
* Correct bool truncstore operand orderChris Lattner2005-12-191-2/+2
* add the other bool zextload as wellChris Lattner2005-12-191-0/+1
* implement zextload boolChris Lattner2005-12-191-0/+3
* Fix syntax for indirect calls. This fixes Olden/mstChris Lattner2005-12-191-2/+2
* apparently rdy isn't actually a psuedo instruction. Use rd %yChris Lattner2005-12-191-1/+1
* add fneg/fabs support for doublesChris Lattner2005-12-191-2/+10
* add bool truncstoresChris Lattner2005-12-191-0/+6
* Configure the asmwriter to allow constant pools to be printed correctlyChris Lattner2005-12-181-1/+0
* add support for integer extloadsChris Lattner2005-12-181-0/+9
* Add support for undefChris Lattner2005-12-181-1/+7
* Change return lowering so that we can autogen the matching code.Chris Lattner2005-12-181-0/+6