aboutsummaryrefslogtreecommitdiffstats
path: root/lib/Target/SystemZ/SystemZRegisterInfo.td
Commit message (Collapse)AuthorAgeFilesLines
* Allocate SystemZ callee-saved registers backwards: R13-R6Jakob Stoklund Olesen2011-06-171-7/+13
| | | | | | | | | The reserved R14-R15 are always saved in the prolog, and using CSRs starting from R13 allows them to be saved in one instruction. Thanks to Anton for explaining this. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133233 91177308-0d34-0410-b5e6-96231b3b80d8
* Use set operations instead of plain lists to enumerate register classes.Jakob Stoklund Olesen2011-06-151-41/+13
| | | | | | | | | | | | This simplifies many of the target description files since it is common for register classes to be related or contain sequences of numbered registers. I have verified that this doesn't change the files generated by TableGen for ARM and X86. It alters the allocation order of MBlaze GPR and Mips FGR32 registers, but I believe the change is benign. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133105 91177308-0d34-0410-b5e6-96231b3b80d8
* Remove custom allocation orders in SystemZ.Jakob Stoklund Olesen2011-06-151-259/+8
| | | | | | | | | | | | | | | | | | Note that this actually changes code generation, and someone who understands this target better should check the changes. - R12Q is now allocatable. I think it was omitted from the allocation order by mistake since it isn't reserved. It as apparently used as a GOT pointer sometimes, and it should probably be reserved if that is the case. - The GR64 registers are allocated in a different order now. The register allocator will automatically put the CSRs last. There were other changes to the order that may have been significant. The test fix is because r0 and r1 swapped places in the allocation order. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133067 91177308-0d34-0410-b5e6-96231b3b80d8
* Remove the DwarfNumbers from the subregisters. They should use DW_OP_bit_pieceRafael Espindola2011-05-301-48/+48
| | | | | | | and for now the generic dwarf emission will automatically use the superregister numbers. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132312 91177308-0d34-0410-b5e6-96231b3b80d8
* Rename TargetFrameInfo into TargetFrameLowering. Also, put couple of FIXMEs ↵Anton Korobeynikov2011-01-101-12/+12
| | | | | | and fixes here and there. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@123170 91177308-0d34-0410-b5e6-96231b3b80d8
* Move hasFP() and few related hooks to TargetFrameInfo.Anton Korobeynikov2010-11-181-24/+24
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119740 91177308-0d34-0410-b5e6-96231b3b80d8
* Merge the SystemZ subreg_even32 SubRegIndex into subreg_32bit. The SubRegIndicesJakob Stoklund Olesen2010-05-281-6/+4
| | | | | | | | | | were overspecified when inheriting sub-subregisters, for instance: R0Q:subreg_even32 = R0Q:subreg_32bit = R0Q:subreg_even:subreg_32bit. This meant that composeSubRegIndices(subreg_even, subreg_32bit) was ambiguous. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@105063 91177308-0d34-0410-b5e6-96231b3b80d8
* Replace the SubRegSet tablegen class with a less error-prone mechanism.Jakob Stoklund Olesen2010-05-261-31/+18
| | | | | | | | | | | | | | | | A Register with subregisters must also provide SubRegIndices for adressing the subregisters. TableGen automatically inherits indices for sub-subregisters to minimize typing. CompositeIndices may be specified for the weirder cases such as the XMM sub_sd index that returns the same register, and ARM NEON Q registers where both D subregs have ssub_0 and ssub_1 sub-subregs. It is now required that all subregisters are named by an index, and a future patch will also require inherited subregisters to be named. This is necessary to allow composite subregister indices to be reduced to a single index. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104704 91177308-0d34-0410-b5e6-96231b3b80d8
* Revert "Replace the SubRegSet tablegen class with a less error-prone mechanism."Jakob Stoklund Olesen2010-05-261-18/+31
| | | | | | This reverts commit 104654. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104660 91177308-0d34-0410-b5e6-96231b3b80d8
* Replace the SubRegSet tablegen class with a less error-prone mechanism.Jakob Stoklund Olesen2010-05-261-31/+18
| | | | | | | | | | | | | | | | A Register with subregisters must also provide SubRegIndices for adressing the subregisters. TableGen automatically inherits indices for sub-subregisters to minimize typing. CompositeIndices may be specified for the weirder cases such as the XMM sub_sd index that returns the same register, and ARM NEON Q registers where both D subregs have ssub_0 and ssub_1 sub-subregs. It is now required that all subregisters are named by an index, and a future patch will also require inherited subregisters to be named. This is necessary to allow composite subregister indices to be reduced to a single index. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104654 91177308-0d34-0410-b5e6-96231b3b80d8
* Remove NumberHack entirely.Jakob Stoklund Olesen2010-05-251-5/+5
| | | | | | | SubRegIndex instances are now numbered uniquely the same way Register instances are - in lexicographical order by name. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104627 91177308-0d34-0410-b5e6-96231b3b80d8
* Switch SubRegSet to using symbolic SubRegIndicesJakob Stoklund Olesen2010-05-241-16/+16
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104571 91177308-0d34-0410-b5e6-96231b3b80d8
* Replace the tablegen RegisterClass field SubRegClassList with an alist-like dataJakob Stoklund Olesen2010-05-241-5/+6
| | | | | | | | | | | structure that represents a mapping without any dependencies on SubRegIndex numbering. This brings us closer to being able to remove the explicit SubRegIndex numbering, and it is now possible to specify any mapping without inventing *_INVALID register classes. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104563 91177308-0d34-0410-b5e6-96231b3b80d8
* Use SubRegIndex in SystemZ.Jakob Stoklund Olesen2010-05-241-5/+7
| | | | | | Anton, please review the change to SystemZAsmPrinter.cpp. It could be a bug. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104515 91177308-0d34-0410-b5e6-96231b3b80d8
* Out GR128 regclass is not a 'real' i128 one.Anton Korobeynikov2009-07-161-1/+1
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@76044 91177308-0d34-0410-b5e6-96231b3b80d8
* Add FP regsAnton Korobeynikov2009-07-161-19/+88
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@76013 91177308-0d34-0410-b5e6-96231b3b80d8
* Provide consistent subreg idx scheme. This (hopefully) fixes remaining ↵Anton Korobeynikov2009-07-161-5/+13
| | | | | | divide problems git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@76011 91177308-0d34-0410-b5e6-96231b3b80d8
* Properly handle divides. As a bonus - implement memory versions of them.Anton Korobeynikov2009-07-161-2/+2
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@76003 91177308-0d34-0410-b5e6-96231b3b80d8
* Add proper register aliasesAnton Korobeynikov2009-07-161-18/+22
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75999 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix thinkoAnton Korobeynikov2009-07-161-8/+6
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75957 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix epic bug with invalid regclass for R0DAnton Korobeynikov2009-07-161-1/+1
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75956 91177308-0d34-0410-b5e6-96231b3b80d8
* More register pairs (now 32 bit ones)Anton Korobeynikov2009-07-161-0/+53
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75954 91177308-0d34-0410-b5e6-96231b3b80d8
* Add even-odd register pairsAnton Korobeynikov2009-07-161-1/+62
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75953 91177308-0d34-0410-b5e6-96231b3b80d8
* Change register allocation order to reduce amount of callee-saved regs to be ↵Anton Korobeynikov2009-07-161-18/+98
| | | | | | spilled. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75944 91177308-0d34-0410-b5e6-96231b3b80d8
* Change register allocation order, so R0 will be allocated the last among ↵Anton Korobeynikov2009-07-161-2/+2
| | | | | | scratch. This will make address-calculation code much more happy. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75928 91177308-0d34-0410-b5e6-96231b3b80d8
* Add shifts and reg-imm address matchingAnton Korobeynikov2009-07-161-0/+54
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75927 91177308-0d34-0410-b5e6-96231b3b80d8
* Add bunch of 32-bit patterns... Uffff :)Anton Korobeynikov2009-07-161-0/+1
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75926 91177308-0d34-0410-b5e6-96231b3b80d8
* Add 32 bit subregsAnton Korobeynikov2009-07-161-21/+82
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75923 91177308-0d34-0410-b5e6-96231b3b80d8
* Add add reg-reg and reg-imm patternsAnton Korobeynikov2009-07-161-1/+9
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75913 91177308-0d34-0410-b5e6-96231b3b80d8
* Let's start another backend :)Anton Korobeynikov2009-07-161-0/+93
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75909 91177308-0d34-0410-b5e6-96231b3b80d8
generated by cgit v1.1 at 2025-11-17 16:56:35 +0000