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* Make insert_subreg a two-address instruction, vastly simplifying LowerSubregs...Christopher Lamb2008-03-161-0/+8
* Remove isImplicitDef TargetInstrDesc flag.Evan Cheng2008-03-151-1/+0
* Replace all target specific implicit def instructions with a target independe...Evan Cheng2008-03-151-0/+7
* Recommitting parts of r48130. These do not appear to cause the observed failu...Christopher Lamb2008-03-111-4/+8
* Revert 48125, 48126, and 48130 for now to unbreak some x86-64 tests.Evan Cheng2008-03-101-8/+4
* Allow insert_subreg into implicit, target-specific values. Christopher Lamb2008-03-101-4/+8
* Rename PrintableName to Name.Bill Wendling2008-02-261-1/+1
* Change "Name" to "AsmName" in the target register info. Gee, a refactoring toolBill Wendling2008-02-261-1/+1
* Some platforms use the same name for 32-bit and 64-bit registers (likeBill Wendling2008-02-241-0/+1
* Move some useful operands up into the all-targets .tdNate Begeman2008-02-141-0/+3
* SDIsel processes llvm.dbg.declare by recording the variable debug information...Evan Cheng2008-02-021-1/+8
* Add an extra operand to LABEL nodes which distinguishes between debug, EH, or...Evan Cheng2008-01-311-1/+1
* Start inferring side effect information more aggressively, and fix many bugs ...Chris Lattner2008-01-101-6/+9
* add a new bit.Chris Lattner2008-01-071-1/+2
* remove a dead field.Chris Lattner2008-01-071-1/+0
* rename isLoad -> isSimpleLoad due to evan's desire to have such a predicate.Chris Lattner2008-01-061-1/+1
* rename isStore -> mayStore to more accurately reflect what it captures.Chris Lattner2008-01-061-1/+1
* Remove attribution from file headers, per discussion on llvmdev.Chris Lattner2007-12-291-2/+2
* As per feedback, revised comments to (hopefully) make the different side effectBill Wendling2007-12-171-3/+12
* Add flags to indicate that there are "never" side effects or that there "may be"Bill Wendling2007-12-141-0/+5
* Implicit def instructions, e.g. X86::IMPLICIT_DEF_GR32, are always re-materia...Evan Cheng2007-12-121-0/+1
* Add a flag for indirect branch instructions.Owen Anderson2007-11-121-0/+1
* Clarify the meaning of '-2' register numberAnton Korobeynikov2007-11-111-2/+4
* Use TableGen to emit information for dwarf register numbers. Anton Korobeynikov2007-11-111-5/+5
* Add CopyCost to TargetRegisterClass. This specifies the cost of copying a valueEvan Cheng2007-09-191-0/+6
* Remove (somewhat confusing) Imp<> helper, use let Defs = [], Uses = [] instead.Evan Cheng2007-09-111-7/+0
* Add target independent MachineInstr's to represent subreg insert/extract in M...Christopher Lamb2007-07-261-0/+12
* No more noResults.Evan Cheng2007-07-211-1/+0
* Change instruction description to split OperandList into OutOperandList andEvan Cheng2007-07-191-6/+14
* It's not necessary to do rounding for alloca operations when the requestedDan Gohman2007-07-181-0/+413