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path: root/lib/Target/TargetSelectionDAG.td
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* Atomic op support. If any gcc test uses __sync builtins, it might start fail...Andrew Lenharth2008-02-211-0/+91
* llvm.memory.barrier, and impl for x86 and alphaAndrew Lenharth2008-02-161-0/+7
* Change how FP immediates are handled. Nate Begeman2008-02-141-2/+1
* Enable SSE4 codegen and pattern matching.Nate Begeman2008-02-111-2/+2
* Tablegen support for insert & extract element matchingNate Begeman2008-02-091-0/+16
* Allow ComplexExpressions in InstrInfo.td files to be slightly more... complex...Christopher Lamb2008-01-311-1/+9
* Factor the addressing mode and the load/store VT out of LoadSDNodeDan Gohman2008-01-301-29/+29
* This commit changes:Chris Lattner2008-01-171-7/+0
* rename SDTRet -> SDTNone.Chris Lattner2008-01-151-2/+4
* add SDNPSideEffect node property declarationChris Lattner2008-01-101-0/+1
* add SDNPMayLoad to the 'load' sdnode definition. This is enough to get all t...Chris Lattner2008-01-101-1/+3
* rename isStore -> mayStore to more accurately reflect what it captures.Chris Lattner2008-01-061-1/+1
* Change the 'isStore' inferrer to look for 'SDNPMayStore' Chris Lattner2008-01-061-2/+5
* Remove attribution from file headers, per discussion on llvmdev.Chris Lattner2007-12-291-2/+2
* add a immAllZerosV_bc pattern fragment for consistency with others.Chris Lattner2007-11-241-3/+6
* Unifacalize the CALLSEQ{START,END} stuff.Bill Wendling2007-11-131-0/+5
* Rename keyword "modify" -> "implicit".Evan Cheng2007-09-251-1/+1
* Initial support for multi-result patterns:Evan Cheng2007-09-121-0/+2
* Long double patch 4 of N: initial x87 implementation.Dale Johannesen2007-08-051-0/+14
* Add selection DAG nodes for subreg insert/extract. PR1350Christopher Lamb2007-07-261-0/+5
* Fix comments about vectors to use the current wording.Dan Gohman2007-07-161-1/+1
* Implement "general dynamic", "initial exec" and "local exec" TLS models forLauro Ramos Venancio2007-04-201-0/+4
* Make LABEL a builtin opcode.Jim Laskey2007-01-261-3/+0
* Fix predicates for unindexed stores so they don't accidentally match indexedChris Lattner2006-11-141-33/+39
* Rename ISD::MemOpAddrMode to ISD::MemIndexedModeEvan Cheng2006-11-091-12/+12
* Added indexed store node and patfrag's.Evan Cheng2006-11-081-11/+131
* Change load PatFrag to ignore indexed load.Evan Cheng2006-10-261-31/+62
* Merge ISD::TRUNCSTORE to ISD::STORE. Switch to using StoreSDNode.Evan Cheng2006-10-131-12/+40
* Add properties to ComplexPattern.Evan Cheng2006-10-111-1/+3
* Naming consistency.Evan Cheng2006-10-111-13/+13
* Reflects ISD::LOAD / ISD::LOADX / LoadSDNode changes.Evan Cheng2006-10-091-16/+74
* Combine ISD::EXTLOAD, ISD::SEXTLOAD, ISD::ZEXTLOAD into ISD::LOADX. Add anEvan Cheng2006-10-041-12/+10
* Vector extract / insert index operand should have ptr type.Evan Cheng2006-06-151-2/+2
* JumpTable support! What this represents is working asm and jit support forNate Begeman2006-04-221-0/+9
* Renamed AddedCost to AddedComplexity.Evan Cheng2006-04-191-4/+4
* Allow "let AddedCost = n in" to increase pattern complexity.Evan Cheng2006-04-191-1/+2
* Add a new vnot_conv predicate for matching vnot's where the allones vector isChris Lattner2006-04-151-0/+6
* Add vector_extract and vector_insert nodes.Evan Cheng2006-03-311-0/+4
* Tblgen doesn't like multiple SDNode<> definitions that map to the sameenum va...Chris Lattner2006-03-281-3/+3
* Changed isBuildVectorAllOnesInteger to isBuildVectorAllOnes.Evan Cheng2006-03-271-1/+1
* Add immAllZerosV helperEvan Cheng2006-03-261-0/+3
* add a vnot helper node for matching 'not' on vectorsChris Lattner2006-03-251-2/+6
* Add new intrinsic node definitions for tblgen useChris Lattner2006-03-251-0/+12
* Shuffle some includes aroundChris Lattner2006-03-241-3/+0
* expose intrinsic info to the targets.Chris Lattner2006-03-241-0/+3
* x86 ISD::SCALAR_TO_VECTOR support.Evan Cheng2006-03-211-0/+2
* Add a build_vector nodeChris Lattner2006-03-201-1/+1
* add vector_shuffleChris Lattner2006-03-201-0/+16
* add support for the bitconvert nodeChris Lattner2006-03-161-0/+3
* relax fcopysignAndrew Lenharth2006-03-091-1/+4
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