aboutsummaryrefslogtreecommitdiffstats
path: root/lib/Target/X86/X86ISelDAGToDAG.cpp
Commit message (Expand)AuthorAgeFilesLines
* Change MachineInstr ctor's to take a TargetInstrDescriptor reference insteadEvan Cheng2006-11-271-9/+10
* For unsigned 8-bit division. Use movzbw to set the lower 8 bits of AX whileEvan Cheng2006-11-171-29/+46
* Removed even more std::cerr and #include <iostream> things.Bill Wendling2006-11-171-20/+14
* Matches MachineInstr changes.Evan Cheng2006-11-131-6/+3
* Add implicit use / def operands to created MI's.Evan Cheng2006-11-111-8/+6
* Add all implicit defs to FP_REG_KILL mi.Evan Cheng2006-11-111-1/+6
* Fix a bug in SelectScalarSSELoad. Since the load is wrapped in aEvan Cheng2006-11-101-0/+1
* Match tblegen changes.Evan Cheng2006-11-081-15/+16
* Unbreak VC++ build.Jeff Cohen2006-11-051-1/+1
* silence warningChris Lattner2006-11-031-6/+0
* SelectScalarSSELoad should call CanBeFoldedBy as well.Evan Cheng2006-10-161-3/+7
* Corrected load folding check. We need to start from the root of the sub-dagEvan Cheng2006-10-141-52/+65
* Merge ISD::TRUNCSTORE to ISD::STORE. Switch to using StoreSDNode.Evan Cheng2006-10-131-1/+1
* Doh. This wasn't causing problems by luck.Evan Cheng2006-10-121-1/+1
* fix compilation failure of smg2000Chris Lattner2006-10-121-1/+1
* Fold "zero extending vector loads" now that evan added the chain manip stuff.Chris Lattner2006-10-111-5/+52
* ComplexPatterns sse_load_f32 and sse_load_f64 returns in / out chain operands.Evan Cheng2006-10-111-7/+10
* More isel time load folding checking for nodes that produce flag values.Evan Cheng2006-10-101-6/+57
* Reflects ISD::LOAD / ISD::LOADX / LoadSDNode changes.Evan Cheng2006-10-091-4/+4
* completely disable folding of loads into scalar sse instructions and provideChris Lattner2006-10-071-0/+25
* Not needed.Evan Cheng2006-09-291-1/+0
* Added some eye-candy for Subtarget type checkingAnton Korobeynikov2006-09-171-1/+1
* Remove a unnecessary check.Evan Cheng2006-09-141-1/+0
* Fix a regression in the 32-bit port from the 64-bit port landing.Chris Lattner2006-09-131-2/+2
* Reflects MachineConstantPoolEntry changes.Evan Cheng2006-09-121-2/+2
* Committing X86-64 support.Evan Cheng2006-09-081-34/+132
* Oops. Bad typo. Without the check of N1.hasOneUse() bad things can happen.Evan Cheng2006-09-011-2/+2
* Remove dead code.Evan Cheng2006-08-291-4/+0
* Don't performance load/op/store transformation if op produces a floating pointEvan Cheng2006-08-291-1/+3
* - Enable x86 isel preprocessing by default unless -fast is specified.Evan Cheng2006-08-291-5/+10
* Avoid making unneeded load/mod/store transformation which can hurt performance.Evan Cheng2006-08-291-5/+10
* Add an optional pass to preprocess the DAG before x86 isel to allow selecting...Evan Cheng2006-08-281-0/+130
* s|llvm/Support/Visibility.h|llvm/Support/Compiler.h|Chris Lattner2006-08-271-1/+1
* Do not use getTargetNode() and SelectNodeTo() which takes more than 3Evan Cheng2006-08-271-4/+4
* SelectNodeTo now returns a SDNode*.Evan Cheng2006-08-261-1/+1
* Select() no longer require Result operand by reference.Evan Cheng2006-08-261-16/+17
* Match tblgen changes; clean up.Evan Cheng2006-08-261-79/+34
* Doh. Incorrectly inverted condition. Also add a isOnlyUse check to match tabl...Evan Cheng2006-08-161-1/+2
* SelectNodeTo() may return a SDOperand that is different from the input.Evan Cheng2006-08-161-2/+1
* Match tablegen changes.Evan Cheng2006-08-111-12/+14
* Eliminate reachability matrix. It has to be calculated before any instructionEvan Cheng2006-08-081-57/+34
* Match tablegen isel changes.Evan Cheng2006-08-071-101/+54
* Reflect change to AssignTopologicalOrder().Evan Cheng2006-08-021-5/+8
* Use of vector<bool> causes some horrendous compile time regression (2x)!Evan Cheng2006-08-021-13/+26
* Factor topological order code to SelectionDAG. Clean up.Evan Cheng2006-08-011-87/+23
* Can't spell.Evan Cheng2006-07-281-15/+15
* Some clean up.Evan Cheng2006-07-281-6/+8
* Rename IsFoldableBy to CanBeFoldedleByEvan Cheng2006-07-281-3/+3
* Node selected into address mode cannot be folded.Evan Cheng2006-07-281-0/+39
* Another duh. Determine topological order before any target node is added.Evan Cheng2006-07-281-13/+13
generated by cgit v1.1 at 2025-01-16 16:52:32 +0000