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path: root/lib/Target/X86/X86ISelLowering.cpp
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* Add DecodeShuffle shuffle support for VPERMIPD variantesBruno Cardoso Lopes2011-07-291-2/+16
* Fix a bug while generating target specific VPERMIL masks: skipBruno Cardoso Lopes2011-07-291-4/+12
* Enable usage of SSE4 extracts and inserts in their 128-bit AVX forms.Bruno Cardoso Lopes2011-07-291-39/+29
* Cleanup PALIGNR handling and remove the old palign pattern fragment.Bruno Cardoso Lopes2011-07-291-6/+2
* Invert the subvector insertion to be more likely to be taken as a COPYBruno Cardoso Lopes2011-07-281-3/+3
* Add SINT_TO_FP and FP_TO_SINT support for v8i32 types. Also moveBruno Cardoso Lopes2011-07-281-0/+3
* Code generation for 'fence' instruction.Eli Friedman2011-07-271-1/+42
* Explicitly cast narrowing conversions inside {}s that will become errors inJeffrey Yasskin2011-07-271-1/+1
* Move some code around to open opportunity for more shuffle matchingBruno Cardoso Lopes2011-07-271-18/+18
* The vpermilps and vpermilpd have different behaviour regarding theBruno Cardoso Lopes2011-07-271-26/+126
* Add a neat little two's complement hack for x86.Benjamin Kramer2011-07-261-3/+30
* Recognize unpckh* masks and match 256-bit versions. The new versions areBruno Cardoso Lopes2011-07-261-32/+59
* Prevent x86-specific DAGCombine from creating nodes with illegal type (which ...Eli Friedman2011-07-261-1/+2
* More movsldup/movshdup cleanup. Rewrite the mask matching function and addBruno Cardoso Lopes2011-07-261-35/+42
* More cleanup, subtarget info isn't used here.Bruno Cardoso Lopes2011-07-261-8/+5
* Codegen allonesvector better while using AVX: vpcmpeqd + vinsertf128Bruno Cardoso Lopes2011-07-251-9/+44
* - Handle special scalar_to_vector case: splats. Using a native 128-bitBruno Cardoso Lopes2011-07-251-1/+39
* Reintroduce r135730, this is indeed the right approach, there is noBruno Cardoso Lopes2011-07-251-0/+18
* Get rid of an incorrect optimization for shuffles with PALIGNR and simplify i...Eli Friedman2011-07-251-15/+5
* Turn shuffles into unpacks for VT == MVT::v2i64 and MVT::v2f64Rafael Espindola2011-07-221-9/+5
* Fix x86's XALUO lowering to return its replacement values insteadDan Gohman2011-07-221-4/+2
* GCC complains about the angle of this line.Benjamin Kramer2011-07-221-1/+1
* Remove the 128-bit special handling from SCALAR_TO_VECTOR. This isn'tBruno Cardoso Lopes2011-07-221-18/+0
* -Inspected a AVX code block added by someone in early Feb. This was never usedBruno Cardoso Lopes2011-07-221-74/+25
* Add a DAGCombine for transforming 128->256 casts into a simpleBruno Cardoso Lopes2011-07-221-7/+61
* Introduce a new function to lower 256-bit vectors which are notBruno Cardoso Lopes2011-07-221-0/+14
* Rename function to be more specific and be more strict about its usageBruno Cardoso Lopes2011-07-221-6/+9
* - Register v16i16 as valid VR256 register classBruno Cardoso Lopes2011-07-211-5/+6
* Add support for 256-bit versions of VPERMIL instruction. This is a newBruno Cardoso Lopes2011-07-211-0/+63
* Improve splat promotion to handle AVX types: v32i8 and v16i16. AlsoBruno Cardoso Lopes2011-07-211-24/+87
* Tidy up codeBruno Cardoso Lopes2011-07-211-15/+5
* Goodbye TargetAsmInfo. This eliminate last bit of CodeGen and Target in llvm-mc.Evan Cheng2011-07-201-5/+2
* Sink getDwarfRegNum, getLLVMRegNum, getSEHRegNum from TargetRegisterInfo downEvan Cheng2011-07-181-3/+3
* land David Blaikie's patch to de-constify Type, with a few tweaks.Chris Lattner2011-07-181-15/+15
* Fix a couple of things:Bruno Cardoso Lopes2011-07-151-61/+52
* Check register class matching instead of width of type matchingEric Christopher2011-07-141-4/+4
* [VECTOR-SELECT]Nadav Rotem2011-07-141-2/+64
* Make X86ISD::ANDNP more general and Codegen 256-bit VANDNP. A moreBruno Cardoso Lopes2011-07-131-3/+5
* The target specific node PANDN name is misleading. That happens becauseBruno Cardoso Lopes2011-07-131-7/+7
* Add _allrem, _aullrem and _allmul to the runtime for MSVC.Julien Lerouge2011-07-081-0/+6
* Add an intrinsic and codegen support for fused multiply-accumulate. The intentCameron Zwarich2011-07-081-0/+6
* Let the inline asm 'q' constraint match float, and on 64-bit double too.Nick Lewycky2011-07-081-3/+3
* Go ahead and emit the barrier on x86-64 even without sse2. TheEric Christopher2011-07-081-3/+4
* Add support for the X86 'l' constraint.Eric Christopher2011-07-071-0/+1
* Use getRegForInlineAsmConstraint instead of custom defining regclassesEric Christopher2011-06-291-52/+24
* Clean up the handling of the x87 fp stack to make it more robust.Jakob Stoklund Olesen2011-06-281-8/+3
* Replace dyn_cast<> with cast<> since the cast is already guarded by the neces...Chad Rosier2011-06-251-1/+1
* Enable tail call optimization in the presence of a byval (x86-32 and x86-64).Chad Rosier2011-06-251-0/+4
* Hoist simple check above more complex checking to avoid unnecessary Chad Rosier2011-06-241-5/+5
* Remove TargetOptions.h dependency from X86Subtarget.Evan Cheng2011-06-231-2/+25
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