| Commit message (Expand) | Author | Age | Files | Lines |
|---|
| * | Speculatively disable Dan's commits 143177 and 143179 to see if | Duncan Sands | 2011-10-28 | 1 | -184/+10 |
| * | Eliminate LegalizeOps' LegalizedNodes map and have it just call RAUW | Dan Gohman | 2011-10-28 | 1 | -10/+184 |
| * | Rename NonScalarIntSafe to something more appropriate. | Lang Hames | 2011-10-26 | 1 | -3/+3 |
| * | Fixes an issue reported by -verify-machineinstrs. | Rafael Espindola | 2011-10-26 | 1 | -4/+5 |
| * | Fix pr11193. | Nadav Rotem | 2011-10-22 | 1 | -3/+0 |
| * | Remove intrinsics for X86 BLSI, BLSMSK, and BLSR intrinsics and replace with ... | Craig Topper | 2011-10-21 | 1 | -1/+53 |
| * | Fix TLS lowering bug. The CopyFromReg must be glued to the TLSCALL. rdar://10... | Evan Cheng | 2011-10-19 | 1 | -1/+2 |
| * | Fix a bunch of unused variable warnings when doing a release | Duncan Sands | 2011-10-18 | 1 | -2/+3 |
| * | SmallVector -> array | Benjamin Kramer | 2011-10-15 | 1 | -3/+3 |
| * | Add X86 ANDN instruction. Including instruction selection. | Craig Topper | 2011-10-14 | 1 | -1/+19 |
| * | Add X86 TZCNT instruction and patterns to select it. Also added core-avx2 pro... | Craig Topper | 2011-10-14 | 1 | -5/+9 |
| * | Revert r141854 because it was causing failures: | Bill Wendling | 2011-10-13 | 1 | -9/+5 |
| * | Add X86 TZCNT instruction and patterns to select it. Also added core-avx2 pro... | Craig Topper | 2011-10-13 | 1 | -5/+9 |
| * | Add X86 LZCNT instruction. Including instruction selection support. | Craig Topper | 2011-10-11 | 1 | -5/+10 |
| * | Make sure the X86 backend doesn't explode on 128-bit shuffles in AVX mode. F... | Eli Friedman | 2011-10-10 | 1 | -12/+4 |
| * | Fix 10892 - When lowering SIGN_EXTEND_INREG do not lower v2i64 because the | Nadav Rotem | 2011-10-10 | 1 | -11/+3 |
| * | High bits of movmskp{s|d} and pmovmskb are known zero. rdar://10247336 | Evan Cheng | 2011-10-07 | 1 | -0/+27 |
| * | PR11033: Make sure we don't generate PCMPGTQ and PCMPEQQ if the target CPU do... | Eli Friedman | 2011-09-28 | 1 | -0/+7 |
| * | Implement Chris's suggestion of legalizing the various SSE and AVX | Duncan Sands | 2011-09-23 | 1 | -0/+13 |
| * | Synthesize SSE3/AVX 128 bit horizontal add/sub instructions from | Duncan Sands | 2011-09-22 | 1 | -0/+150 |
| * | The SSE version differences for fmin/fmax are more involved than I thought. | Benjamin Kramer | 2011-09-22 | 1 | -3/+4 |
| * | X86: Don't form min/max nodes if the target is missing SSE. | Benjamin Kramer | 2011-09-22 | 1 | -1/+2 |
| * | fix comment | Nadav Rotem | 2011-09-21 | 1 | -1/+1 |
| * | Insert a sanity check on the combining of x86 truncing-store nodes. This come... | Nadav Rotem | 2011-09-21 | 1 | -0/+3 |
| * | Change: | Richard Trieu | 2011-09-21 | 1 | -2/+2 |
| * | Simplify max/minp[s|d] dagcombine matching | Bruno Cardoso Lopes | 2011-09-20 | 1 | -6/+3 |
| * | Extend changes from r139986 to produce 256-bit AVX minps/minpd/maxps/maxpd. | Craig Topper | 2011-09-20 | 1 | -3/+6 |
| * | Fix typos in my prev commit, found by Tobi. | Nadav Rotem | 2011-09-18 | 1 | -2/+2 |
| * | setOperationAction should be done on the return value of the type, not the op... | Nadav Rotem | 2011-09-18 | 1 | -1/+1 |
| * | When promoting integer vectors we often create ext-loads. This patch adds a | Nadav Rotem | 2011-09-18 | 1 | -3/+86 |
| * | Fix typo by changing Lower256IntVETCC to Lower256IntVSETCC. | Craig Topper | 2011-09-18 | 1 | -3/+3 |
| * | Synthesize x86 max/min instructions also for vectors (i.e. produce | Duncan Sands | 2011-09-17 | 1 | -4/+7 |
| * | Change all checks regarding the presence of any SSE level to always | Bruno Cardoso Lopes | 2011-09-15 | 1 | -62/+75 |
| * | Fix the code creating VZEXT_LOAD so that it creates the right memoperand. Is... | Eli Friedman | 2011-09-14 | 1 | -3/+6 |
| * | Vector shuffle mask <i32 4, i32 5, i32 2, i32 3> should yield "movsd", not "m... | Bruno Cardoso Lopes | 2011-09-14 | 1 | -1/+3 |
| * | Revert the remaining part of r139528. According to PR10907 the bug seems | Bruno Cardoso Lopes | 2011-09-13 | 1 | -5/+5 |
| * | Add vselect target support for targets that do not support blend but do support | Nadav Rotem | 2011-09-13 | 1 | -0/+1 |
| * | Revert the wrong part of r139528, and fix testcases. | Bruno Cardoso Lopes | 2011-09-12 | 1 | -4/+4 |
| * | Not sure how CMPPS and CMPPD had already ever worked, I guess it didn't. | Bruno Cardoso Lopes | 2011-09-12 | 1 | -9/+18 |
| * | CR fixes per Bruno's request. | Nadav Rotem | 2011-09-11 | 1 | -53/+14 |
| * | r139454 activates an assert in a case where we were doing the right thing any... | Eli Friedman | 2011-09-10 | 1 | -1/+9 |
| * | Fixed an assert from: | Richard Trieu | 2011-09-10 | 1 | -1/+1 |
| * | Implement vector-select support for avx256. Refactor the vblend implementatio... | Nadav Rotem | 2011-09-09 | 1 | -8/+20 |
| * | Dix the 80-columns and remove unsupported v8i16 type from the list of legal v... | Nadav Rotem | 2011-09-08 | 1 | -9/+12 |
| * | Add AVX versions of blend vector operations and fix some issues noticed | Bruno Cardoso Lopes | 2011-09-08 | 1 | -1/+1 |
| * | Add X86-SSE4 codegen support for vector-select. | Nadav Rotem | 2011-09-08 | 1 | -0/+34 |
| * | Add codegen support for vector select (in the IR this means a select | Duncan Sands | 2011-09-06 | 1 | -16/+20 |
| * | Fix style issues and typos found by Duncan. | Rafael Espindola | 2011-09-06 | 1 | -3/+3 |
| * | Split the init.trampoline intrinsic, which currently combines GCC's | Duncan Sands | 2011-09-06 | 1 | -10/+13 |
| * | Use existing function. | Jakob Stoklund Olesen | 2011-09-02 | 1 | -7/+3 |
