aboutsummaryrefslogtreecommitdiffstats
path: root/lib/Target/X86/X86ISelLowering.h
Commit message (Expand)AuthorAgeFilesLines
* Rename NonScalarIntSafe to something more appropriate.Lang Hames2011-10-261-2/+2
* Remove intrinsics for X86 BLSI, BLSMSK, and BLSR intrinsics and replace with ...Craig Topper2011-10-211-0/+4
* Add X86 ANDN instruction. Including instruction selection.Craig Topper2011-10-141-0/+2
* Synthesize SSE3/AVX 128 bit horizontal add/sub instructions fromDuncan Sands2011-09-221-0/+6
* CR fixes per Bruno's request.Nadav Rotem2011-09-111-1/+0
* Implement vector-select support for avx256. Refactor the vblend implementatio...Nadav Rotem2011-09-091-4/+2
* Add X86-SSE4 codegen support for vector-select.Nadav Rotem2011-09-081-1/+4
* Fix comment. Noticed by Duncan.Rafael Espindola2011-09-061-1/+1
* Add codegen support for vector select (in the IR this means a selectDuncan Sands2011-09-061-2/+2
* Split the init.trampoline intrinsic, which currently combines GCC'sDuncan Sands2011-09-061-1/+2
* Adds support for variable sized allocas. For a variable sized alloca,Rafael Espindola2011-08-301-0/+4
* Adds a SelectionDAG node X86SegAlloca which will be custom loweredRafael Espindola2011-08-301-0/+5
* Add support for generating CMPXCHG16B on x86-64 for the cmpxchg IR instruction.Eli Friedman2011-08-261-1/+2
* Break 256-bit vector int add/sub/mul into two 128-bit operations to avoid cos...Craig Topper2011-08-241-1/+3
* Introduce matching patterns for vbroadcast AVX instruction. The idea is toBruno Cardoso Lopes2011-08-171-0/+1
* The VPERM2F128 is a AVX instruction which permutes between two 256-bitBruno Cardoso Lopes2011-08-121-0/+1
* Cleanup PALIGNR handling and remove the old palign pattern fragment.Bruno Cardoso Lopes2011-07-291-4/+0
* Code generation for 'fence' instruction.Eli Friedman2011-07-271-0/+1
* The vpermilps and vpermilpd have different behaviour regarding theBruno Cardoso Lopes2011-07-271-1/+4
* Recognize unpckh* masks and match 256-bit versions. The new versions areBruno Cardoso Lopes2011-07-261-0/+2
* More movsldup/movshdup cleanup. Rewrite the mask matching function and addBruno Cardoso Lopes2011-07-261-2/+2
* -Inspected a AVX code block added by someone in early Feb. This was never usedBruno Cardoso Lopes2011-07-221-2/+0
* Add support for 256-bit versions of VPERMIL instruction. This is a newBruno Cardoso Lopes2011-07-211-0/+1
* land David Blaikie's patch to de-constify Type, with a few tweaks.Chris Lattner2011-07-181-4/+4
* [VECTOR-SELECT]Nadav Rotem2011-07-141-0/+1
* The target specific node PANDN name is misleading. That happens becauseBruno Cardoso Lopes2011-07-131-2/+2
* Use getRegForInlineAsmConstraint instead of custom defining regclassesEric Christopher2011-06-291-4/+0
* Remove TargetOptions.h dependency from X86Subtarget.Evan Cheng2011-06-231-0/+6
* Add a parameter to CCState so that it can access the MachineFunction.Eric Christopher2011-06-081-3/+4
* Followup to 132458, omit unnecessary stack copy when x87 input is aStuart Hastings2011-06-061-2/+3
* Reapply 132424 with fixes. This fixes PR10068.Stuart Hastings2011-06-031-0/+5
* Have LowerOperandForConstraint handle multiple character constraints.Eric Christopher2011-06-021-1/+1
* Revert 132424 to fix PR10068.Rafael Espindola2011-06-021-5/+0
* Recommit 132404 with fixes. rdar://problem/5993888Stuart Hastings2011-06-011-0/+5
* Revert 132404 to appease a buildbot. rdar://problem/5993888Stuart Hastings2011-06-011-5/+0
* Add support for x86 CMPEQSS and friends. These instructions do aStuart Hastings2011-06-011-0/+5
* FGETSIGN support for x86, using movmskps/pd. Will be enabled with aStuart Hastings2011-06-011-0/+5
* Reverting 132105: it broke some LLVM-GCC DejaGNU tests.Stuart Hastings2011-05-261-2/+0
* Correctly handle a one-word struct passed byval on x86_64.Stuart Hastings2011-05-261-0/+2
* Clean up the mess created by r131467+r131469.Eli Friedman2011-05-171-4/+0
* Revert 131467 due to buildbot complaint.Stuart Hastings2011-05-171-2/+4
* Fix an obscure issue in X86_64 parameter passing: if a tiny byval isStuart Hastings2011-05-171-0/+2
* Add custom lowering of X86 vector SRA/SRL/SHL when the shift amount is a spla...Nadav Rotem2011-05-111-2/+2
* Make the logic for determining function alignment more explicit. No function...Eli Friedman2011-05-061-3/+0
* Re-apply r127953 with fixes: eliminate empty return block if it has no predec...Evan Cheng2011-03-211-0/+2
* Revert r127953, "SimplifyCFG has stopped duplicating returns into predecessorsDaniel Dunbar2011-03-191-2/+0
* SimplifyCFG has stopped duplicating returns into predecessors to canonicalize IREvan Cheng2011-03-191-0/+2
* Move more logic into getTypeForExtArgOrReturn.Cameron Zwarich2011-03-171-2/+3
* Rename getTypeForExtendedInteger() to getTypeForExtArgOrReturn().Cameron Zwarich2011-03-171-1/+1
* The x86-64 ABI says that a bool is only guaranteed to be sign-extended to a byteCameron Zwarich2011-03-161-0/+3
generated by cgit v1.1 at 2024-09-12 10:10:52 +0000