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* Update aosp/master LLVM for rebase to r230699.Stephen Hines2015-03-231-825/+1120
| | | | Change-Id: I2b5be30509658cb8266be782de0ab24f9099f9b9
* Update aosp/master LLVM for rebase to r222494.Stephen Hines2014-12-021-1077/+1714
| | | | Change-Id: Ic787f5e0124df789bd26f3f24680f45e678eef2d
* Update LLVM for rebase to r212749.Stephen Hines2014-07-211-67/+234
| | | | | | | Includes a cherry-pick of: r212948 - fixes a small issue with atomic calls Change-Id: Ib97bd980b59f18142a69506400911a6009d9df18
* Update LLVM for 3.5 rebase (r209712).Stephen Hines2014-05-291-24/+182
| | | | Change-Id: I149556c940fb7dc92d075273c87ff584f400941f
* Update to LLVM 3.5a.Stephen Hines2014-04-241-859/+1535
| | | | Change-Id: Ifadecab779f128e62e430c2b4f6ddd84953ed617
* AVX-512: Handled extractelement from mask vector;Elena Demikhovsky2013-11-141-0/+33
| | | | | | | Added VMOSHDUP/VMOVSLDUP shuffle instructions. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194691 91177308-0d34-0410-b5e6-96231b3b80d8
* Add support for AVX512 masked vector blend intrinsics.Cameron McInally2013-11-041-15/+39
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194006 91177308-0d34-0410-b5e6-96231b3b80d8
* AVX-512: added VPCONFLICT instruction and intrinsics,Elena Demikhovsky2013-11-031-0/+70
| | | | | | | added EVEX_KZ to tablegen git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@193959 91177308-0d34-0410-b5e6-96231b3b80d8
* Add AVX512 unmasked integer broadcast intrinsics and support.Cameron McInally2013-10-311-0/+10
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@193748 91177308-0d34-0410-b5e6-96231b3b80d8
* AVX-512: PMIN/PMAX intrinsics and patternsElena Demikhovsky2013-10-271-0/+28
| | | | | | | Patch by Cameron McInally <cameron.mcinally@nyu.edu> git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@193497 91177308-0d34-0410-b5e6-96231b3b80d8
* [X86][AVX512] Add patterns that match the AVX512 floating point register ↵Quentin Colombet2013-10-251-0/+5
| | | | | | | | | vbroadcast intrinsics. Patch by Cameron McInally <cameron.mcinally@nyu.edu> git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@193422 91177308-0d34-0410-b5e6-96231b3b80d8
* [X86][AVX512] Add patterns that match the AVX512 floating point vbroadcast ↵Quentin Colombet2013-10-251-0/+5
| | | | | | | | | intrinsics. Patch by Cameron McInally <cameron.mcinally@nyu.edu> git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@193421 91177308-0d34-0410-b5e6-96231b3b80d8
* AVX-512: added VCVTPH2PS, VCVTPS2PH with intrinsicsElena Demikhovsky2013-10-241-0/+36
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@193312 91177308-0d34-0410-b5e6-96231b3b80d8
* AVX-512: aligned / unaligned load and store for 512-bit integer vectors.Elena Demikhovsky2013-10-221-30/+35
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@193156 91177308-0d34-0410-b5e6-96231b3b80d8
* X86 vector element shift-by-immediate instructions take i8 immediates. MakeLang Hames2013-10-211-6/+6
| | | | | | | | | | | | | | | | the instruction defenitions and ISEL reflect this. Prior to this patch these instructions took an i32i8imm, and the high bits were dropped during encoding. This led to incorrect behavior for shifts by immediates higher than 255. This patch fixes that issue by detecting large immediate shifts and returning constant zero (for logical shifts) or capping the shift amount at an encodable value (for arithmetic shifts). Fixes <rdar://problem/14968098> git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@193096 91177308-0d34-0410-b5e6-96231b3b80d8
* Remove more filters from the disassembler. Mark some AVX512 instructions as ↵Craig Topper2013-10-121-0/+6
| | | | | | CodeGenOnly. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192525 91177308-0d34-0410-b5e6-96231b3b80d8
* AVX-512: Added VRCP28 and VRSQRT28 instructions and intrinsics.Elena Demikhovsky2013-10-091-33/+86
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192283 91177308-0d34-0410-b5e6-96231b3b80d8
* Add missing HasAVX512 predicate.Andrew Trick2013-10-091-2/+2
| | | | | | | This was only working because AVX had cheaper rules in all cases. I'm sure there are other places in this file where predicates are missing. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192276 91177308-0d34-0410-b5e6-96231b3b80d8
* Use AVX512PIi8 for the alt forms of vcmp instructions. This adds the TB ↵Craig Topper2013-10-091-4/+4
| | | | | | prefix and keeps the mnemonic from starting with an extra 'v' git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192272 91177308-0d34-0410-b5e6-96231b3b80d8
* AVX-512: added scalar convert instructions and intrinsics.Elena Demikhovsky2013-10-061-8/+174
| | | | | | | Fixed load folding in VPERM2I instruction. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192063 91177308-0d34-0410-b5e6-96231b3b80d8
* AVX-512: fixed shuffle loweringElena Demikhovsky2013-10-061-1/+11
| | | | | | | in case of BLEND and added VSHUFPS patterns. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192055 91177308-0d34-0410-b5e6-96231b3b80d8
* AVX-512: Fixed encoding of VMOVQ instruction.Elena Demikhovsky2013-10-031-3/+3
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191889 91177308-0d34-0410-b5e6-96231b3b80d8
* AVX-512: fixed a bug in getLoadStoreRegOpcode() for AVX-512 targetElena Demikhovsky2013-10-021-2/+2
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191818 91177308-0d34-0410-b5e6-96231b3b80d8
* AVX-512: Added TB prefix to all instructions without prefixes,Elena Demikhovsky2013-10-021-17/+15
| | | | | | | otherwise encoding fails after the last change in X86MCCodeEmitter.cpp. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191812 91177308-0d34-0410-b5e6-96231b3b80d8
* AVX-512: Added X86vzmovl patternsElena Demikhovsky2013-10-011-0/+5
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191733 91177308-0d34-0410-b5e6-96231b3b80d8
* Put HasAVX512 predicate on some patterns to properly disable them when ↵Craig Topper2013-09-271-9/+11
| | | | | | AVX512 isn't enabled. Currently it works simply because the SSE and AVX version of the same patterns are checked first in the DAG isel table. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191490 91177308-0d34-0410-b5e6-96231b3b80d8
* AVX-512: Converted to Unix styleElena Demikhovsky2013-09-171-3070/+3070
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@190851 91177308-0d34-0410-b5e6-96231b3b80d8
* Adds support for Atom Silvermont (SLM) - -march=slmPreston Gurd2013-09-131-8/+8
| | | | | | | | | | | | | | Implements Instruction scheduler latencies for Silvermont, using latencies from the Intel Silvermont Optimization Guide. Auto detects SLM. Turns on post RA scheduler when generating code for SLM. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@190717 91177308-0d34-0410-b5e6-96231b3b80d8
* AVX-512: implemented extractelement with variable index.Elena Demikhovsky2013-09-121-3058/+3070
| | | | | | | Added parsing of mask register and "zeroing" semantic, like {%k1} {z}. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@190595 91177308-0d34-0410-b5e6-96231b3b80d8
* AVX-512: Added GATHER and SCATTER instructions.Elena Demikhovsky2013-09-011-0/+63
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@189729 91177308-0d34-0410-b5e6-96231b3b80d8
* AVX-512: added extend and truncate instructions.Elena Demikhovsky2013-08-291-0/+117
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@189580 91177308-0d34-0410-b5e6-96231b3b80d8
* AVX-512: added SQRT, VRSQRT14, VCOMISS, VUCOMISS, VRCP14, VPABSElena Demikhovsky2013-08-281-0/+443
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@189472 91177308-0d34-0410-b5e6-96231b3b80d8
* AVX-512: added conversion instructions.Elena Demikhovsky2013-08-271-0/+187
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@189349 91177308-0d34-0410-b5e6-96231b3b80d8
* AVX-512: Added FMA instructions.Elena Demikhovsky2013-08-271-0/+197
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@189326 91177308-0d34-0410-b5e6-96231b3b80d8
* AVX-512: Added shuffle instructions - Elena Demikhovsky2013-08-261-2/+137
| | | | | | | | VPSHUFD, VPERMILPS, VMOVDDUP, VMOVLHPS, VMOVHLPS, VSHUFPS, VALIGN single and double forms. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@189215 91177308-0d34-0410-b5e6-96231b3b80d8
* AVX-512: added UNPACK instructions and tests for all-zero/all-ones vectorsElena Demikhovsky2013-08-251-0/+62
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@189189 91177308-0d34-0410-b5e6-96231b3b80d8
* AVX-512: Added masked SHIFT commands, more encoding testsElena Demikhovsky2013-08-221-18/+38
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@189005 91177308-0d34-0410-b5e6-96231b3b80d8
* AVX-512: Added SHIFT instructions.Elena Demikhovsky2013-08-211-0/+141
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@188899 91177308-0d34-0410-b5e6-96231b3b80d8
* AVX-512: Added more patterns for VMOVSS, VMOVSD, VMOVD, VMOVQElena Demikhovsky2013-08-201-11/+70
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@188786 91177308-0d34-0410-b5e6-96231b3b80d8
* AVX-512: added arithmetic and logical operations.Elena Demikhovsky2013-08-191-15/+232
| | | | | | | | ADD, SUB, MUL integer and FP types. OR, AND, XOR. Added embeded broadcast form for these instructions. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@188673 91177308-0d34-0410-b5e6-96231b3b80d8
* AVX-512: Added VMOVD, VMOVQ, VMOVSS, VMOVSD instructions.Elena Demikhovsky2013-08-181-7/+270
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@188637 91177308-0d34-0410-b5e6-96231b3b80d8
* Don't use v16i32 for load pattern matching. All 512-bit loads are cated to ↵Craig Topper2013-08-161-7/+7
| | | | | | v8i64. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@188534 91177308-0d34-0410-b5e6-96231b3b80d8
* AVX-512: Added CMP and BLEND instructions.Elena Demikhovsky2013-08-131-0/+202
| | | | | | | Lowering for SETCC. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@188265 91177308-0d34-0410-b5e6-96231b3b80d8
* AVX-512: Added VPERM* instructons and MOV* zmm-to-zmm instructions.Elena Demikhovsky2013-08-111-0/+237
| | | | | | | Added a test for shuffles using VPERM. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@188147 91177308-0d34-0410-b5e6-96231b3b80d8
* AVX-512 set: Added BROADCAST instructionsElena Demikhovsky2013-08-071-0/+126
| | | | | | | with lowering logic and a test. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187884 91177308-0d34-0410-b5e6-96231b3b80d8
* AVX-512 set: added mask operations, lowering BUILD_VECTOR for i1 vector types.Elena Demikhovsky2013-08-051-0/+241
| | | | | | | Added intrinsics and tests. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187717 91177308-0d34-0410-b5e6-96231b3b80d8
* AVX-512 set: added VEXTRACTPS instructionElena Demikhovsky2013-08-041-5/+14
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187705 91177308-0d34-0410-b5e6-96231b3b80d8
* Added INSERT and EXTRACT intructions from AVX-512 ISA.Elena Demikhovsky2013-07-311-0/+339
All insertf*/extractf* functions replaced with insert/extract since we have insertf and inserti forms. Added lowering for INSERT_VECTOR_ELT / EXTRACT_VECTOR_ELT for 512-bit vectors. Added lowering for EXTRACT/INSERT subvector for 512-bit vectors. Added a test. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187491 91177308-0d34-0410-b5e6-96231b3b80d8